Buffer Descriptor Pointer Register; Dma Control Register - Digi NS7520B-1-C36 Hardware Reference Manual

D M A c h a n n e l r e g i s t e r s

Buffer Descriptor Pointer register

Address: FF90 0000 / 20 / 40 / 60 / 80 / A0 / C0 / E0 / 100 / 120 / 140 / 160 / 180 / 1A0 / 1C0 / 1E0
The Buffer Descriptor Pointer register contains the address of the first buffer
descriptor in a contiguous list of descriptors.
DMA channel 1 is unique in that it supports four different buffer descriptors: A, B, C,
and D. Each buffer descriptor contains a separate ring of descriptors, and identifies a
block of data buffers with a different size. This feature allows the Ethernet receiver
to choose the optimum buffer size for the incoming packet.
31 30
15 14

DMA Control register

Address: FF90 0010 / 30 / 50 / 70 / 90 / B0 / D0 / F0 / 110 / 130 / 150 / 170 / 190 / 1B0 / 1D0 / 1F0
31 30
CE CA
15 14
Register bit assignment
Bits
D31
Table 50: DMA Control register bit definition
1 3 6
29 28 27 26
13 12 11 10
29 28 27 26
BB MODE
13 12 11 10
STATE
Access Mnemonic Reset
R/W CE 0
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
25 24 23 22 21
Buffer descriptor pointer
9 8 7 6 5
Buffer descriptor pointer
25 24 23 22 21
BTE REQ RSVD SINC_
9 8 7 6 5
INDEX
Description
DMA channel enable
Set only after the other channel mode bits are set. The DMA
channel begins reading the first buffer descriptor when CE
is set to 1.
20 19 18 17 16
4 3 2 1 0
20 19 18 17 16
DINC_ Reserved SIZE
4 3 2 1 0