Setting The Pll Frequency; Pll Settings Register: Setting The Pll Frequency On Bootup - Digi NS7520B-1-C36 Hardware Reference Manual

S e t t i n g t h e P L L f r e q u e n c y

Setting the PLL frequency

Three fields — IS (charge pump current), FS (output divider), and ND (PLL
multiplier) — in the PLL Settings register control the behavior of the PLL circuit. You
cannot write to the PLL Settings register directly, however; it is configured in one of
these ways:
On bootup, the PLL Settings register is configured by reading the values on
1
address lines A[8:0]. The address lines have internal pullups. The normally high
values can be changed to 0 by connecting 2.7K pulldown resistors.
The PLL Settings register is configured by writing to the PLL Control register.
2
Only the ND field can be reconfigured this way.

PLL Settings register: Setting the PLL frequency on bootup

The PLL Settings register, FFB0 0040, is initialized at bootup by reading address lines
A[8:0]. Only the ND field can be changed by writing a new bus speed to the PLLCNT
register in the PLL Control register.
31 30
15 14
Bits
D31:09
Table 21: PLL Settings register bit definition
5 4
29 28 27 26
13 12 11 10
Reserved
Access Mnemonic Reset
N/A Reserved N/
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
25 24 23 22 21
Reserved
9 8 7 6 5
IS FS
Description
N/A
20 19 18 17 16
4 3 2 1 0
ND