Ethernet Interface Mac - Digi NS7520B-1-C36 Hardware Reference Manual

P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s
Mnemonic
OE_
Table 5: Chip select controller signal description

Ethernet interface MAC

Note:
In this table, GP designates general-purpose.
Symbol
MII
MDC
MDIO
TXCLK
TXD3
TXD2
TXD1
TXD0
TXER
TXEN
TXCOL
RXCRS
RXCLK
RXD3
Table 6: Ethernet interface MAC pinout
1 8
Signal
Output enable
ENDEC values for general-purpose output and TXD refer to bits in the
Ethernet General Control register. ENDEC values for general-purpose input
and RXD refer to bits in the Ethernet General Status register.
Pin
ENDEC
GP output D10
GP output B10 U
C10
GP output A12
GP output B11
GP output D11
TXD A11
GP output A13
B12
A14
D12
C12
GP input D14
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Description
Active low signal that indicates that a memory read cycle is
in progress. This signal is activated only during read cycles
from peripherals controlled by one of the chip selects in the
memory module.
I/O OD Description
MII
O 2 MII management
clock
I/O 2 MII data
I TX clock
O 2 TX data 3
O 2 TX data 2
O 2 TX data 1
O 2 TX data 0
O 2 TX code error
O 2 TX enable
I Collision
I Carrier sense
I RX clock
I RX data 3
ENDEC
State of (LPBK bit XOR
(Mode=SEEQ))
State of UTP_STP bit
State of AUI_TP[0] bit
State of AUI_TP[1] bit
Inverted state of PDN bit,
open collector
Transmit data
State of LNK_DIS_ bit
Read state in bit 12