Ethernet Fifo Data Register - Digi NS7520B-1-C36 Hardware Reference Manual

Data bit
D15
D13
D12
D11
D10
Table 56: ENDEC status signal cross-reference

Ethernet FIFO Data register

Address: FF80 0008 / FF80 000C (secondary address)
The Ethernet FIFO Data register allows manual interface with the Ethernet FIFO,
rather than using DMA support. This register is used primarily as a diagnostic tool.
Writing to the Ethernet FIFO Data register
Writing to the Ethernet FIFO Data register loads the transmit FIFO. This register can
be written only when the TXREGE bit is set in the Ethernet General Status register,
indicating that space is available in the transmit FIFO.
The transmit FIFO has a secondary address
transmit frame. The first and middle words must use the primary address
(FF80 0008)
Writing to the secondary address with the transmit interrupts disabled (ETXBC in the
Ethernet General Control register) initiates transmission of data from the transmit
FIFO. Otherwise, transmission begins when the TX FIFO byte count equals the
selected watermark (ETXWM in the Ethernet General Control register).
Reading from the Ethernet FIFO Data register
Reading from the Ethernet FIFO Data register empties the receive FIFO. The Ethernet
General Status register indicates how many bytes are available to be read. The
receive FIFO is available only when the RXBR bit has been set to 1, which clears the
bit, in the Ethernet General Status register.
NS7520 pin
RXD2
RXD1
RXD3
RXER
RXDV
.
that signifies the last word of a
(FF80 000C)
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