Digi NS7520B-1-C36 Hardware Reference Manual page 291

SDRAM burst read
SDRAM read, CAS latency = 2
T1
prechg
BCLK
TA* (Note-5)
TEA*/LAST* (Note-5)
PortA2/AMUX
6
Non-muxed address
35
Muxed address
36
BE*[3:0]* (DQM)
read D[31:0]
27
CS[4:0]*
34
CAS3* (RAS)
CAS2* (CAS)
34
CAS1* (WE)
CAS0* (A10/AP)
12
RW*
Notes:
Port size determines which byte enable signals are active:
1
8-bit port = BE3*
–
16-bit port = BE[3:2]
–
– 32-bit port = BE[3:0]
The precharge and/or active commands are not always present. These
2
commands depend on the address of the previous SDRAM access.
If CAS latency = 3, 5 NOPs occur between the read and burst terminate
3
commands.
If CAS latency = 3, 3 inhibits occur after burst terminate.
4
The TA* and TEA*/LAST signals are for reference only.
5
T2
active read nop nop
30
37 37
35
10
34
34 34
34
34 34 34
A10
w w w . d i g i e m b e d d e d . c o m
E l e c t r i c a l C h a r a c t e r i s t i c s
T2 T2 T2
nop nop bterm inhibit
30
31 31
36
11
27
34 34
T1
inhibit
2 7 9