T i m i n g D i a g r a m s
External DMA timing
BCLK max frequency: 55.296 MHz
Operating conditions:
Temperature:
Voltage:
Output load:
Input drive:
External DMA timing parameters
Num
72
75
70
71
73
74
2 9 4
-15.00 (min)
110.00 (max)
1.60 (min)
1.40 (max)
25.0pf
CMOS buffer
Description
BCLK high to DACK* valid
BCLK high to DONE* (output) valid
DREQ* low to BCLK high (setup)
BCLK high to DREQ* valid (hold)
DONE* (input) valid BCLK high (setup)
BLCK high to DONE* (input) valid (hold)
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Min
Max
Unit
14
ns
15
ns
5
ns
0
ns
5
ns
0
ns
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