Digi NS7520B-1-C36 Hardware Reference Manual page 283

SRAM write
CS controlled write (internal and external), (wait = 2)
T1
BCLK
TA* (Note-4)
TEA* (Note-4)
TA* (input)
6
A[27:0]
36
Note-2
BE[3:0]*
CS[4:0]*
write D[31:0]
Sync WE*
CS0WE*
12
RW*
Notes:
If the next transfer is DMA, null periods between memory transfers can occur.
1
Thirteen clock pulses are required for DMA context switching.
Port size determines which byte enable signals are active:
2
8-bit port = BE3*
–
16-bit port = BE[3:0]
–
32-bit port = BE[3:0]
–
The TW cycles are present when the WAIT field is set to 2 or more.
3
The TA* and TEA*/LAST signals are for reference only.
4
TW TW
27
9
29
19
w w w . d i g i e m b e d d e d . c o m
E l e c t r i c a l C h a r a c t e r i s t i c s
T2 Note-1
30 30
31 31
15
14
36
27
13
29
19
T1
2 7 1