Digi NS9215 Hardware Reference Manual

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NS9215

Hardware Reference

90000847_C

Release date: 10 April 2008

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Page 1: Hardware Reference
NS9215 Hardware Reference 90000847_C Release date: 10 April 2008...
Page 2 Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of fitness or merchantability for a particular purpose. Digi may make improvements and/or changes in this manual or in the product(s) and/or the program(s) described in this manual at any time.
Page 5: Table Of Contents
Contents ..............C h a p t e r 1 : P i n o u t ( 2 6 5 ) .
Page 6 R0: ID code and cache type status registers ... 86 R0: ID code ... 86 R0: Cache type register... 86 Cache type register and field description ... 87 Dsize and Isize fields ... 87 R1: Control register ... 88 Control register ... 89 Bit functionality... 89 Hardware Reference NS9215...
Page 7: Chapter 1 3 : I 2 C M A S T E R / S L A V E I N T E R F A C
R2: Translation Table Base register...91 R3:Domain Access Control register...91 R4 register ...92 R5: Fault Status registers ...92 R6: Fault Address register ...93 R7:Cache Operations register ...94 R8:TLB Operations register...97 R9: Cache Lockdown register ...98 R10:TLB Lockdown register ... 101 R11 and R12 registers ... 102 R13:Process ID register ...
Page 8 Second-level descriptor pages ...114 Second-level descriptor bit assignments ...115 Second-level descriptor least significant bits ...115 Translation sequence for large page references...116 Translating sequence for small page references ...117 Translation sequence for tiny page references ...118 Subpages ...118 Hardware Reference NS9215 [1:0]...111...
Page 9 MMU faults and CPU aborts... 119 Domain access control ... 121 Fault checking sequence... 122 External aborts ... 125 Enabling and disabling the MMU ... 125 TLB structure ... 126 Caches and write buffer ... 127 Cache MVA and Set/Way formats ... 130 Noncachable instruction fetches ...
Page 10 PLL configuration and control system block diagram ...152 Bootstrap initialization ...152 Configuring the powerup settings ...152 System configuration registers ...154 Register address map ...154 General Arbiter Control register ...158 BRC0, BRC1, BRC2, and BRC3 registers ...158 Channel allocation...159 AHB Error Detect Status 1 ...159 Hardware Reference NS9215...
Page 11 AHB Error Detect Status 2 ... 160 AHB Error Monitoring Configuration register ... 161 Timer Master Control register ... 162 Timer 0–4 Control registers... 164 Timer 5 Control register ... 166 Timer 6–9 Control registers... 168 Timer 6–9 High registers ... 170 Timer 6–9 Low registers...
Page 12 Read followed by write with no turnaround...219 Write followed by a read with no turnaround...220 Read followed by a write with two turnaround cycles...220 Byte lane control ...221 Address connectivity ...222 Memory banks constructed from 8-bit or non-byte-partitioned memory devices Hardware Reference NS9215...
Page 13 Dynamic memory controller... 225 SDRAM Initialization ... 225 SDRAM address and data bus interconnect ... 228 Registers ... 230 Control register ... 232 Status register ... 234 Configuration register... 234 Dynamic Memory Control register ... 235 Dynamic Memory Refresh Timer register... 236 Dynamic Memory Read Configuration register ...
Page 14 Interrupts ...273 Interrupt sources ...273 Status bits...274 Resets ...274 Multicast address filtering ...275 Filter entries ...275 Multicast address filter registers ...275 Multicast address filtering example 1 ...275 Multicast address filtering example 2 ...276 Notes ...276 Clock synchronization...276 Hardware Reference NS9215...
Page 15 Ethernet Control and Status registers ... 277 Ethernet General Control Register #1 ... 279 Ethernet General Control Register #2 ... 282 Ethernet General Status register ... 283 Ethernet Transmit Status register... 284 Ethernet Receive Status register ... 286 MAC Configuration Register #1... 288 MAC Configuration Register #2...
Page 16 Multicast Address Filter registers ...327 Multicast Low Address Filter Register #0...327 Multicast Low Address Filter Register #1...327 Multicast Low Address Filter Register #2...327 Multicast Low Address Filter Register #3...327 Multicast Low Address Filter Register #4...327 Multicast Low Address Filter Register #5...327 Hardware Reference NS9215...
Page 17 Multicast Address Mask registers ... 329 Multicast Address Filter Enable register... 331 TX Buffer Descriptor RAM... 332 RX FIFO RAM ... 333 Sample hash table code... 334 C h a p t e r 7 : E x t e r n a l D M A ..........3 3 9 DMA transfers...
Page 18 AES DMA buffer descriptor ...356 AES buffer descriptor diagram...357 Source address [pointer] ...357 Source buffer length ...357 Destination buffer length...357 Destination address [pointer] ...357 AES control ...357 AES op code...358 WRAP (W) bit ...358 Interrupt (I) bit...358 Hardware Reference NS9215...
Page 19 Decryption ... 359 ECB processing ... 359 CBC, CFB, OFB, and CTR processing ... 360 CCM mode... 360 C h a p t e r 9 : I / O H u b M o d u l e ..........3 6 3 DMA controller ...
Page 20 Force Transmit Character Control register ...402 ARM Wakeup Control register...403 Transmit Byte Count ...404 UART Receive Buffer ...405 UART Transmit Buffer...405 UART Baud Rate Divisor LSB ...406 UART Baud Rate Divisor MSB ...406 UART Interrupt Enable register...407 UART Interrupt Identification register ...408 Hardware Reference NS9215...
Page 21 UART FIFO Control register... 409 UART Line Control register ... 409 UART Modem Control register ... 411 UART Line Status register ... 411 UART Modem Status register ... 412 C h a p t e r 1 1 : S e r i a l C o n t r o l M o d u l e : H D L C ......4 1 5 Receive and transmit operations ...
Page 22 Locked interrupt driven mode ...449 Master module and slave module commands...449 Bus arbitration ...449 I2C registers ...450 Register address map ...450 Command Transmit Data register ...450 Register ...450 Register bit assignment ...451 Status Receive Data register...451 Register ...451 Hardware Reference NS9215...
Page 23 Master Address register ... 452 Slave Address register... 453 Configuration register... 454 Interrupt Codes ... 455 Software driver... 456 Flow charts ... 457 C h a p t e r 1 4 : R e a l T i m e C l o c k M o d u l e ....... . . 4 5 9 RTC configuration and status registers ...
Page 24 SPI master mode2 and 3: 2-byte transfer ...507 SPI slave mode 0 and 1: 2-byte transfer ...508 SPI slave mode 2 and 3: 2-byte transfer ...508 Reset and hardware strapping timing ...509 JTAG timing ...510 Hardware Reference NS9215 C timing ...504...
Page 25 Clock timing ... 511 C h a p t e r 1 7 : P a c k a g i n g ........... . . 5 1 3 Package...
Page 26 Hardware Reference NS9215...
Page 27: Chapter 1 : P I N O U T ( 2 6 5 )
Pinout (265) he NS9215 offers a connection to a 10/100 Ethernet network, as well as a glueless connection to SDRAM, PC100 DIMM, flash, EEPROM, and SRAM memories, and an external bus expansion module. It includes four multi-function serial ports, one I2C channel, 12-bit Analog to Digital converter, battery backed real time clock and an AES data encryption/decryption module.
Page 28: Memory Bus Interface
Hardware Reference NS9215 Description SDRAM bus clock SDRAM bus clock Address bus, Endian Address bus, SPI boot Address bus Address bus, Boot width [1] Address bus, Boot width [0] Address bus...
Page 29 Signal addr[0] data[31] data[30] data[29] data[28] data[27] data[26] data[25] data[24] data[23] data[22] data[21] data[20] data[19] data[18] data[17] data[16] data[15] / gpio[31] data[14] / gpio[30] data[13] / gpio[29] data[12] / gpio[28] data[11] / gpio[27] data[10] / gpio[26] data[9] / gpio[25] data[8] / gpio[24] data[7] / gpio[23] data[6] / gpio[22] data[5] / gpio[21]...
Page 30: Ethernet Interface Mac
................. . Signal mdc / gpio[32] mdio / gpio[35] tx_clk / gpio[33] txd[3] / gpio[47] Hardware Reference NS9215 Description byte_enable data[31:24} Byte enable data[23:16] Byte enable data[15:08] Byte enable data {07:00]...
Page 31: General Purpose I/O (Gpio)
Signal txd[2] / gpio[46] txd[1] / gpio[45] txd[0] / gpio[44] tx_er / gpio[43] tx_en / gpio[42] col / gpio[48] crs / gpio[49] rx_clk / gpio[34] rxd[3] / gpio[41] rxd[2] / gpio[40] rxd[1] / gpio[39] rxd[0] / gpio[38] rx_er / gpio[37] rx_dv / gpio[36] G e n e r a l p u r p o s e I / O ( G P I O ) .
Page 32 2, reset_done. GPIO 16 to 31 are reset to mode 0, external memory data 15:0. Signal gpio[0] gpio[1] gpio[2] gpio[3] gpio[4] gpio[5] gpio[6] gpio[7] Hardware Reference NS9215 Description DCD UART A Ext DMA Done Ch 0 PIC_0_GEN_IO[0](I/O) gpio[0] SPI EN (dup) CTS UART A Ext Int 0 PIC_0_GEN_IO[1](I/O) gpio[1]...
Page 33 Signal gpio[8] gpio[9] gpio[10] gpio[11] gpio[12] gpio[13] gpio[14] gpio[15] www.digiembedded.com Description DCD / TXC UART C Ext DMA Done Ch 1 Ext Timer Event Out Ch 8 gpio[8] SPI EN (dup) CTS UART C C SCL Ext Int Ch 0 (dup) gpio[9] PIC_DBG_DATA_IN(I) DSR UART C...
Page 34 General purpose I/O (GPIO) Signal gpio[16] gpio[17] gpio[18] gpio[19] gpio[20] gpio[21] gpio[22] gpio[23] gpio[24] gpio[25] Hardware Reference NS9215 Description data[0] DCD UART B Ext Int Ch 0 (dup) gpio[16] data[1] CTS UART B Ext Int Ch 1 (dup) gpio[17] data[2] DSR UART B...
Page 35 Signal gpio[26] gpio[27] gpio[28] gpio[29] gpio[30] gpio[31] gpio[32] gpio[33] gpio[34] gpio[35] www.digiembedded.com Description data[10] DSR UART D PIC_1_GEN_IO[0](I/O) gpio[26] data[11] RXD UART D PIC_1_GEN_IO[1](I/O) gpio[27] data[12] RI UART D PIC_1_GEN_IO[2](I/O) gpio[28] data[13] RTS / RS485 Control UART D PIC_1_GEN_IO[3](I/O) gpio[29] data[14] TXC / DTR UART D Reserved...
Page 36 P I N O U T ( 2 6 5 ) General purpose I/O (GPIO) Signal gpio[36] gpio[37] gpio[38] gpio[39] gpio[40] gpio[41] gpio[42] gpio[43] gpio[44] gpio[45] Hardware Reference NS9215 Description Ethernet MII RX DV PIC_0_GEN_IO[4](I/O)(dup) Reserved gpio[36] Ethernet MII RX ER PIC_0_GEN_IO[5](I/O)(dup) Reserved gpio[37] Ethernet MII RXD[0] PIC_0_GEN_IO[6](I/O)(dup) Reserved...
Page 37 Signal gpio[46] gpio[47] gpio[48] gpio[49] gpio[50] gpio[51] gpio[52] gpio[53] gpio[54] gpio[55] www.digiembedded.com Description Ethernet MII TXD[2] PIC_1_GEN_IO[6](I/O)(dup) Reserved gpio[46] Ethernet MII TXD[3] PIC_1_GEN_IO[7](I/O)(dup) Reserved gpio[47] Ethernet MII COL Reserved Reserved gpio[48] Ethernet MII CRS Reserved Reserved gpio[49] Ethernet MII PHY Int PIC_1_CLK(I) PIC_1_CLK(O) gpio[50]...
Page 38 General purpose I/O (GPIO) Signal gpio[56] gpio[57] gpio[58] gpio[59] gpio[60] gpio[61] gpio[62] gpio[63] gpio[64] gpio[65] Hardware Reference NS9215 Description RTS/RS485 Control UART B (dup) PIC_0_BUS_1[13](I/O) PIC_1_BUS_1[13](I/O) gpio[56] TXC/DTR UART B (dup) PIC_0_BUS_1[14](I/O) PIC_1_BUS_1[14](I/O) gpio[57] TXD UART B (dup) PIC_0_BUS_1[15](I/O) PIC_1_BUS_1[15](I/O)
Page 39 Signal gpio[66] gpio[67] gpio[68] gpio[69] gpio[70] gpio[71] gpio[72] gpio[73] gpio[74] gpio[75] www.digiembedded.com Description TXD UART D (dup) PIC_0_BUS_1[23](I/O) PIC_1_BUS_1[23](I/O) gpio[66] PIC_0_CLK(I) PIC_0_CLK(O) Ext Int Ch 3 (dup) gpio[67] PIC_0_GEN_IO[0](I/O)(dup) PIC_1_GEN_IO[0](I/O) PIC_1_CAN_RXD(I)(dup) gpio[68] PIC_0_GEN_IO[1](I/O)(dup) PIC_1_GEN_IO[1](I/O) PIC_1_CAN_TXD(O)(dup) gpio[69] PIC_0_GEN_IO[2](I/O)(dup) PIC_1_GEN_IO[2](I/O) PWM Ch 0 gpio[70] PIC_0_GEN_IO[3](I/O)(dup) PIC_1_GEN_IO[3](I/O)
Page 40 General purpose I/O (GPIO) Signal gpio[76] gpio[77] gpio[78] gpio[79] gpio[80] gpio[81] gpio[82] gpio[83] gpio[84] gpio[85] Hardware Reference NS9215 Description PIC_0_CTL_IO[0](I/O) PIC_1_CTL_IO[0](I/O) Ext Timer Event in Ch 2 gpio[76] PIC_0_CTL_IO[1](I/O) PIC_1_CTL_IO[1](I/O) Ext Timer Event in Ch 3 gpio[77] PIC_0_CTL_IO[2](I/O) PIC_1_CTL_IO[2](I/O) Ext Timer Event in Ch 4...
Page 41 Signal gpio[86] gpio[87] gpio[88] gpio[89] gpio[90] gpio[91] gpio[92] gpio[93] gpio[94] gpio[95] www.digiembedded.com Description PIC_0_BUS_0[6](I/O) PIC_1_BUS_0[6](I/O) Ext Timer Event Out Ch 2 gpio[86] PIC_0_BUS_0[7](I/O) PIC_1_BUS_0[7](I/O) Ext Timer Event Out Ch 3 gpio[87] PIC_0_BUS_0[8](I/O) PIC_1_BUS_0[8](I/O) Ext Timer Event Out Ch 4 gpio[88] PIC_0_BUS_0[9](I/O) PIC_1_BUS_0[9](I/O) Ext Timer Event Out Ch 5...
Page 42 P I N O U T ( 2 6 5 ) General purpose I/O (GPIO) Signal gpio[96] gpio[97] gpio[98] gpio[99] gpio[100] gpio[101] gpio[102] gpio[103] gpio_a[0] gpio_a[1] Hardware Reference NS9215 Description PIC_0_BUS_1[0](I/O) PIC_1_BUS_1[0](I/O) PIC_0_CAN_RXD(I)(dup) gpio[96] PIC_0_BUS_1[1](I/O) PIC_1_BUS_1[1](I/O) PIC_0_CAN_TXD(O)(dup) gpio97 PIC_0_BUS_1[2](I/O) PIC_1_BUS_1[2](I/O) PIC_1_CAN_RXD(I)(dup)
Page 43: System Clock
Signal gpio_a[2] gpio_a[3] a. There is a possible conflict when gpio12 is used as the I2C_SDA signal. in this case the I2C_SDA signal is driven low while in reset, then driven active high after end of reset, until software configures this pin for the I2C function. S y s t e m c l o c k .
Page 44: System Clock Drawing
P I N O U T ( 2 6 5 ) System clock System clock drawing Hardware Reference NS9215...
Page 45: Rtc Clock And Battery Backup Drawing
RTC clock and battery backup drawing Note: If RTC battery backup is not used, the following connection changes can be made. N3, M4 32.788kHz S y s t e m m o d e ................. . www.digiembedded.com bat_vdd_reg tie to 1.8V...
Page 46 P I N O U T ( 2 6 5 ) System mode sys_mode_2 sys_mode_1 Hardware Reference NS9215 sys_mode_0 Description manufacturing test manufacturing test manufacturing test normal operation, boundary scan enabled, POR disabled normal operation, boundary scan enabled, POR enabled...
Page 47: System Reset
– soft reset input buffer with pull-up resistor, does not reset the PLL reset_out_n – hardware reset to NS9215 core and output buffer, resets all logic in NS9215 core including PLL reset_done – reflects the state of the ARM926 reset, for any type of reset event www.digiembedded.com...
Page 48: Jtag Test
................. . Signal trst_n rtck Hardware Reference NS9215 Description Test data in Test data out Test mode select Test mode reset.
Page 49: Adc
A D C ................. . If the ADC feature is not used, the inputs must be terminated as shown below: www.digiembedded.com Signal...
Page 50: Por And Battery-Backed Logic
M13, sys_mode [2.0] M14, Hardware Reference NS9215 Description POR reference ground POR VSS POR VDD (3.3V) POR reference trip voltage (2.74V min / 2.97V max) POR early power loss voltage (1.19V min / 1.28V max)
Page 51: Power And Ground
If the RTC feature is not used, the inputs must be terminated as shown below. N3, M4 If the RTC feature is used, see RTC clock and battery backup drawing on page 45. P o w e r a n d g r o u n d .
Page 52 P I N O U T ( 2 6 5 ) Power and ground Hardware Reference NS9215...
Page 53: Chapter 2 : I / O C O N T R O L M O D U L E
I/O Control Module he NS9215 ASIC contains 108 pins that are designated as general purpose I/O (GPIO). The first 16 GPIO can be configured to serve one of five functions. The remaining GPIO can be configured to serve one of four functions.
Page 54 A090_206C A090_2070 A090_2074 A090_2078 A090_207C A090_2080 A090_2084 A090_2088 Hardware Reference NS9215 Description GPIO Configuration Register #3 GPIO Configuration Register #4 GPIO Configuration Register #5 GPIO Configuration Register #6 GPIO Configuration Register #7 GPIO Configuration Register #8 GPIO Configuration Register #9...
Page 55: Gpio Configuration Registers
The reset values for all the status bits are undefined because they depend on the state of the GPIO pins to NS9215. G P I O C o n f i g u r a t i o n r e g i s t e r s .
Page 56: Gpio Configuration Register #0
GPIO Configuration Register #0 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_2004 GPIO Configuration Register #1 Bit(s) D31:24 D23:16 D15:08 D07:00 Hardware Reference NS9215 GPIO3 GPIO1 Access Mnemonic Reset GPIO3 0x18 GPIO2 0x18 GPIO1 0x18 GPIO0 0x18 GPIO7 GPIO5 Access Mnemonic...
Page 57: Gpio Configuration Register #2
Address: A090_2008 GPIO Configuration Register #2 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_200C GPIO Configuration Register #3 Bit(s) D31:24 D23:16 D15:08 D07:00 www.digiembedded.com GPIO11 GPIO9 Access Mnemonic Reset GPIO11 0x18 GPIO10 0x18 GPIO9 0x18 GPIO8 0x18 GPIO15 GPIO13 Access Mnemonic Reset GPIO15 0x18...
Page 58: Gpio Configuration Register #4
GPIO Configuration Register #4 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_2014 GPIO Configuration Register #5 Bit(s) D31:24 D23:16 D15:08 D07:00 Hardware Reference NS9215 GPIO19 GPIO17 Access Mnemonic Reset GPIO19 0x00 GPIO18 0x00 GPIO17 0x00 GPIO16 0x00 GPIO23 GPIO21 Access Mnemonic...
Page 59: Gpio Configuration Register #6
Address: A090_2018 GPIO Configuration Register #6 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_201C GPIO Configuration Register #7 Bit(s) D31:24 D23:16 D15:08 D07:00 www.digiembedded.com GPIO27 GPIO25 Access Mnemonic Reset GPIO27 0x00 GPIO26 0x00 GPIO25 0x00 GPIO24 0x00 GPIO39 GPIO37 Access Mnemonic Reset GPIO31 0x00...
Page 60: Gpio Configuration Register #8
GPIO Configuration Register #8 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_2024 GPIO Configuration Register #9 Bit(s) D31:24 D23:16 D15:08 D07:00 Hardware Reference NS9215 GPIO35 GPIO33 Access Mnemonic Reset GPIO35 0x18 GPIO34 0x18 GPIO33 0x18 GPIO32 0x18 GPIO39 GPIO37 Access Mnemonic...
Page 61: Gpio Configuration Register #10
Address: A090_2028 GPIO Configuration Register #10 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_202C GPIO Configuration Register #11 Bit(s) D31:24 D23:16 D15:08 D07:00 www.digiembedded.com GPIO43 GPIO41 Access Mnemonic Reset GPIO43 0x18 GPIO42 0x18 GPIO41 0x18 GPIO40 0x18 GPIO47 GPIO45 Access Mnemonic Reset GPIO47 0x18...
Page 62: Gpio Configuration Register #12
GPIO Configuration Register #12 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_2034 GPIO Configuration Register #13 Bit(s) D31:24 D23:16 D15:08 D07:00 Hardware Reference NS9215 GPIO51 GPIO49 Access Mnemonic Reset GPIO51 0x18 GPIO50 0x18 GPIO49 0x18 GPIO48 0x18 GPIO55 GPIO53 Access Mnemonic...
Page 63: Gpio Configuration Register #14
Address: A090_2038 GPIO Configuration Register #14 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_203C GPIO Configuration Register #15 Bit(s) D31:24 D23:16 D15:08 D07:00 www.digiembedded.com GPIO59 GPIO57 Access Mnemonic Reset GPIO59 0x18 GPIO58 0x18 GPIO57 0x18 GPIO56 0x18 GPIO63 GPIO61 Access Mnemonic Reset GPIO63 0x18...
Page 64: Gpio Configuration Register #16
GPIO Configuration Register #16 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_2044 GPIO Configuration Register #17 Bit(s) D31:24 D23:16 D15:08 D07:00 Hardware Reference NS9215 GPIO67 GPIO65 Access Mnemonic Reset GPIO67 0x18 GPIO66 0x18 GPIO65 0x18 GPIO64 0x18 GPIO71 GPIO69 Access Mnemonic...
Page 65: Gpio Configuration Register #18
Address: A090_2048 GPIO Configuration Register #18 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_204C GPIO Configuration Register #19 Bit(s) D31:24 D23:16 D15:08 D07:00 www.digiembedded.com GPIO75 GPIO73 Access Mnemonic Reset GPIO75 0x18 GPIO74 0x18 GPIO73 0x18 GPIO72 0x18 GPIO79 GPIO77 Access Mnemonic Reset GPIO79 0x18...
Page 66: Gpio Configuration Register #20
GPIO Configuration Register #20 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_2054 GPIO Configuration Register #21 Bit(s) D31:24 D23:16 D15:08 D07:00 Hardware Reference NS9215 GPIO83 GPIO81 Access Mnemonic Reset GPIO83 0x18 GPIO82 0x18 GPIO81 0x18 GPIO80 0x18 GPIO87 GPIO85 Access Mnemonic...
Page 67: Gpio Configuration Register #22
Address: A090_2058 GPIO Configuration Register #22 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_205C GPIO Configuration Register #23 Bit(s) D31:24 D23:16 D15:08 D07:00 www.digiembedded.com GPIO91 GPIO89 Access Mnemonic Reset GPIO91 0x18 GPIO90 0x18 GPIO89 0x18 GPIO88 0x18 GPIO95 GPIO93 Access Mnemonic Reset GPIO95 0x18...
Page 68: Gpio Configuration Register #24
GPIO Configuration Register #24 Bit(s) D31:24 D23:16 D15:08 D07:00 Address: A090_2064 GPIO Configuration Register #25 Bit(s) D31:24 D23:16 D15:08 D07:00 Hardware Reference NS9215 GPIO99 GPIO97 Access Mnemonic Reset GPIO99 0x18 GPIO98 0x18 GPIO97 0x18 GPIO96 0x18 GPIO103 GPIO101 Access Mnemonic...
Page 69: Gpio Configuration Register #26
Address: A090_2068 GPIO Configuration Register #26 Bit(s) D31:24 D23:16 D15:08 D07:00 www.digiembedded.com GPIO_A3 GPIO_A1 Access Mnemonic Reset GPIO_A3 0x18 GPIO_A2 0x18 GPIO_A1 0x18 GPIO_A0 0x18 I / O C O N T R O L M O D U L E GPIO Configuration registers GPIO_A2 GPIO_A0...
Page 70: Gpio Control Registers
GPIO Control Registers #0 through #3 is driven out the GPIO pin. In all configurations, the CPU has read/write access to these registers. Address: A090_206C GPIO Control Register #0 Bit(s) Access Hardware Reference NS9215 Mnemonic Reset Description GPIO0 GPIO[0] control bit GPIO1...
Page 71: Gpio Control Register #1
Bit(s) Address: A090_2070 GPIO Control Register #1 Bit(s) www.digiembedded.com Access Mnemonic Reset GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 Access Mnemonic Reset GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52...
Page 72: Gpio Control Register #2
I / O C O N T R O L M O D U L E GPIO Control registers Bit(s) Access Address: A090_2074 GPIO Control Register #2 Bit(s) Access Hardware Reference NS9215 Mnemonic Reset Description GPIO54 GPIO[54] control bit GPIO55 GPIO[55] control bit GPIO56...
Page 73: Gpio Control Register #3
Bit(s) Address: A090_2078 GPIO Control Register #3 Bit(s) D31:12 www.digiembedded.com Access Mnemonic Reset GPIO83 GPIO84 GPIO85 GPIO86 GPIO87 GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 GPIO95 Access Mnemonic Reset GPIO96 GPIO97 GPIO98 GPIO99 GPIO100 GPIO101 GPIO102 GPIO103 GPIO_A0 GPIO_A1 GPIO_A2 GPIO_A3 Reserved I / O C O N T R O L M O D U L E...
Page 74: Gpio Status Registers
108 GPIO pins. In all configurations, the value on the GPIO input pin is brought to the status register and the CPU has read-only access to the register. Address: A090_2080 GPIO Status Register #1 Bit(s) Access Hardware Reference NS9215 Mnemonic Reset Description GPIO32 Undefined GPIO[32] status bit...
Page 75: Gpio Status Register #2
Bit(s) Address: A090_2084 GPIO Status Register #2 Bit(s) www.digiembedded.com Access Mnemonic Reset GPIO58 Undefined GPIO59 Undefined GPIO60 Undefined GPIO61 Undefined GPIO62 Undefined GPIO63 Undefined Access Mnemonic Reset GPIO64 Undefined GPIO65 Undefined GPIO66 Undefined GPIO67 Undefined GPIO68 Undefined GPIO69 Undefined GPIO70 Undefined GPIO71 Undefined...
Page 76: Gpio Status Register #3
................. . The Memory Bus Configuration register controls chip select and upper address options. Address: A090_208C Hardware Reference NS9215 Mnemonic Reset Description...
Page 77 Bit(s) D02:00 D05:03 D08:06 D11:09 www.digiembedded.com Access Mnemonic Reset I / O C O N T R O L M O D U L E Memory Bus Configuration register Description Controls which system memory chip select is routed to CS0 dy_cs_0 dy_cs_1 dy_cs_2...
Page 78 I / O C O N T R O L M O D U L E Memory Bus Configuration register Bit(s) Access D14:12 D17:15 D20:18 D23:21 Hardware Reference NS9215 Mnemonic Reset Description Controls which system memory chip select is routed to CS4 dy_cs_0 dy_cs_1...
Page 79 Bit(s) D31:26 www.digiembedded.com Access Mnemonic Reset APUDIS Reserved I / O C O N T R O L M O D U L E Memory Bus Configuration register Description Address bus pullup control (Applicable only to address associated with hardware strapping) Enable pullup resistors Disable pullup resistors Note:...
Page 80 I / O C O N T R O L M O D U L E Memory Bus Configuration register Hardware Reference NS9215...
Page 81: Working With The Cpu
Working with the CPU his processor core is based on the ARM926EJ-S processor. The ARM926EJ-S processor belongs to the ARM9 family of general-purpose microprocessors. The ARM926EJ-S processor is targeted at multi-tasking applications in which full memory management, high performance, low die size, and low power are important. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instructions About the sets, allowing you to trade off between high performance and high code density.
Page 82: Arm926Ej-S Process Block Diagram
The Thumb instruction set is simpler than the ARM instruction set, and offers Thumb increased code density for code that does not require maximum performance. Code instruction set can switch between ARM and Thumb instruction sets on any procedure call. Hardware Reference NS9215 DEXT Write buffer DROUTE DCACHE...
Page 83: Java Instruction Set
In Java state, the processor core executes a majority of Java bytecodes naturally. Java instruction Bytecodes are decoded in two states, compared to a single decode stage when in ARM/Thumb mode. See “Jazelle(Java)” on page 104 for more information about Java.
Page 84: Terms And Abbreviations
Term UNPREDICTABLE UNDEFINED SHOULD BE ZERO SHOULD BE ONE SHOULD BE ZERO or PRESERVED Hardware Reference NS9215 21 20 19 16 15 Opcode results. In all instructions that access CP15: field , except when the values specified are used SHOULD BE ZERO...
Page 85: Register Summary
In all cases, reading from or writing any data values to any CP15 registers, Note: including those fields specified as BE ZERO, CP15 uses 16 registers. Register summary Register locations 0, 5, and 13 each provide access to more than one register. The register accessed depends on the value of the MRC/MCR Register location 9 provides access to more than one register.
Page 86: R0: Id Code And Cache Type Status Registers
See “Cache features” on page 127 for more information about cache. Hardware Reference NS9215 BIGENDINIT signal is high. ID value instruction and data cache type when reading from these registers.
Page 87: Cache Type Register And Field Description
You can access the cache type register by reading CP15 register R0 with the field set to 1. Note this example: Cache type register and field description Field Ctype S bit Dsize Isize The Dsize and Isize fields in the cache type register have the same format, as Dsize and Isize shown: fields...
Page 88: R1: Control Register
The V bit is set to zero at reset if the The B bit is set to zero at reset if the BIGENDINIT Hardware Reference NS9215 Description Determines the cache size in conjunction with the M bit. The M bit is 0 for DCache and ICache.
Page 89: Control Register
Control register Bit functionality Bits [31:19] [18] [17] [16] [15] [14] [13] [12] [11:10] www.digiembedded.com 18 17 16 15 14 13 Name Function Reserved: When read, returns an When written, [31:19] on the same processor. Use a read-modify-write sequence when modifying this register to provide the greatest future compatibility.
Page 90: Icache And Dcache Behavior
If either the DCache or ICache is disabled, the contents of that cache are not accessed. If the cache subsequently is re-enabled, the contents will not have changed. To guarantee that memory coherency is maintained, the DCache must be cleaned of dirty data before it is disabled. Hardware Reference NS9215 Name Function Reserved.
Page 91: R2: Translation Table Base Register
R 2 : T r a n s l a t i o n T a b l e B a s e r e g i s t e r ................. . Register R2 is the Translation Table Base register (TTBR), for the base address of the first-level translation table.
Page 92: R4 Register
Register bits Bits [31:9] [7:4] [3:0] Hardware Reference NS9215 Data Fault Status register (DFSR) Instruction Fault Status register (IFSR) MRC p15, 0, Rd, c5, c0, 0; read DFSR MCR p15, 0, Rd, c5, c0, 0; write DFSR MRC p15, 0, Rd, c5, c0, 1; read IFSR MCR p15, 0, Rd, c5, c0, 1;...
Page 93: Status And Domain Fields
This table shows the encodings used for the status field in the Fault Status register, Status and and indicates whether the domain field contains valid information. See “MMU faults domain fields and CPU aborts” on page 119 for information about MMU aborts in Fault Address and Fault Status registers.
Page 94: R7:Cache Operations Register
Clean and invalidate single data entry using wither index or modified virtual address. Test and clean DCache Test, clean, and invalidate DCache Prefetch ICache line Hardware Reference NS9215 fields in the opcode_2 opcode_2 , with the exception of the two test and clean...
Page 95: Cache Operation Functions
Function Drain write buffer Wait for interrupt This table lists the cache operation functions and associated data and instruction Cache operation formats for R7. functions Function/operation Invalidate ICache and DCache Invalidate ICache Invalidate ICache single entry (MVA) Invalidate ICache single entry (set/way) Prefetch ICache line (MVA) Invalidate DCache Invalidate DCache single entry (MVA)
Page 96: Modified Virtual Address Format (Mva)
DCache to determine whether any of them are dirty. If any dirty lines are found, one of those lines is cleaned. The test and clean DCache instruction also returns the status of the entire DCache in bit 30. Hardware Reference NS9215 Data format SHOULD BE ZERO...
Page 97: Test, Clean, And Invalidate Dcache Instruction
The test and clean DCache instruction Note: encoding that uses using this instruction, however. This code flags. If the cache contains any dirty lines, bit 30 is set to 0. If the cache contains no dirty lines, bit 30 is set to 1. Use the following loop to clean the entire cache: The test, clean, and invalidate DCache instruction is the same as the test and clean Test, clean, and DCache instruction except that when the entire cache has been cleaned, it is...
Page 98: Modified Virtual Address Format (Mva)
If no cache ways have the L bit set to 0, cache way 3 is used for all linefills. Note: Hardware Reference NS9215 Data Instruction MCR p15, 0, Rd, c8, c6, 0...
Page 99: Instruction Or Data Lockdown Register
The first four bits of this register determine the L bit for the associated cache way. Instruction or The opcode_2 field of the MRC or MCR instruction determines whether the data lockdown register instruction or data lockdown register is accessed: opcode_2=0 opcode_2=1 Use these instructions to access the CacheLockdown register.
Page 100: Lockdown Cache: Specific Loading Of Addresses Into A Cache-Way
– If an ICache is being locked down, use the Cache Operations register (R7) prefetch ICache line into the cache. Hardware Reference NS9215 4-way associative Notes L bit for way 3 Bits [3:0] are the L bits for each cache way:...
Page 101: Cache Unlock Procedure
Write restoring all other bits to the values they had before the lockdown routine was started. To unlock the locked down portion of the cache, write to Cache Lockdown register Cache unlock (R9) setting procedure the L bit to 0 for way 0 of the ICache, unlocking way 0: R 1 0 : T L B L o c k d o w n r e g i s t e r .
Page 102: Programming Instructions
................. . The Process ID register accesses the process identifier registers. The register accessed depends on the value on the opcode_2=0 Hardware Reference NS9215 Instruction MRC p15, 0, Rd, c10, c0, 0 MCR p15, 0, Rd, c10, c0, 0...
Page 103: Fcse Pid Register
opcode_2=1 Use the Process ID register to determine the process that is currently running. The process identifier is set to 0 at reset. Addresses issued by the ARM926EJ-S core, in the range 0 to 32 MB, are translated FCSE PID according to the value contained in the FCSE PID register.
Page 104: Context Id Register
Java Virtual Machine (JVM) software layer has been written to work with the Jazelle hardware. The Java byte code acceleration is accomplished by the following: Hardware, which directly executes 80% of simple Java byte codes. Hardware Reference NS9215 Data ARM instruction Context ID...
Page 105: Dsp
Software emulation within the ARM-optimized JVM, which addresses the remaining 20% of the Java byte codes. D S P ................. . The ARM926EJ-S processor core provides enhanced DSP capability.
Page 106: Access Permissions And Domains
When retrieved, the translation information is written into the TLB, possible overwriting an existing value. At reset, the MMU is turned off, no address mapping occurs, and all regions are marked as noncachable and nonbufferable. Hardware Reference NS9215...
Page 107: Mmu Program Accessible Registers
This table shows the CP15 registers that are used in conjunction with page table MMU program descriptors stored in memory to determine MMU operation. accessible registers Register R1: Control register R2: Translation Table Base register R3: Domain Access Control register R5: Fault Status registers, IFSR and DFSR R6: Fault Address register...
Page 108: Translation Table Base
The translation table has up to 4096 x 32-bit entries, each describing 1 MB of virtual memory. This allows up to 4 GB of virtual memory to be addressed. Hardware Reference NS9215 on a read, and the table must reside on a 16 KB boundary.
Page 109: Table Walk Process
Table walk process TTB base Indexed by modified virtual address bits [31:20] Bits [31:14] of the TTB register are concatenated with bits [31:20] of the MVA to First-level fetch produce a 30-bit address. www.digiembedded.com Translation Section table Section base Indexed by modified virtual address...
Page 110: First-Level Fetch Concatenation And Address
Coarse page tables, which have 256 entries and split the 1 MB that the table describes into 4 KB blocks. Fine page tables, which have 1024 entries and split the 1 MB that the table describes into 1 KB blocks. Hardware Reference NS9215 Modified virtual address 20 19 Table index...
Page 111: First-Level Descriptor Bit Assignments: Priority Encoding Of Fault Status
First-level Bits descriptor bit assignments: Section Priority encoding of fault status [31:20] [19:12] [11:10] [8:5] [3:2] [1:0] First-level Value descriptor bit assignments: Interpreting first level descriptor bits [1:0] A section descriptor provides the base address of a 1 MB block of memory. Section descriptor Section descriptor format...
Page 112: Section Descriptor Bit Description
A fine page table descriptor provides the base address of a page table that contains Fine page table second-level descriptors for large page, small page, or tiny page accesses. Fine descriptor Hardware Reference NS9215 Description Forms the corresponding bits of the physical address for a section. Always written as 0.
Page 113: Fine Page Table Descriptor Format
page tables have 1024 entries, splitting the 1 MB that the table describes into 1 KB blocks. The next two sections show the format of a fine page table descriptor and define the fine page table descriptor bit assignments. If a fine page table descriptor is returned from the first-level fetch, a Note: second-level fetch is initiated.
Page 114: Second-Level Descriptor
A large page descriptor provides the base address of a 64 KB block of memory. A small page descriptor provides the base address of a 4 KB block of memory. Hardware Reference NS9215 20 19 Table index Translation table base...
Page 115: Second-Level Descriptor Bit Assignments
A tiny page descriptor provides the base address of a 1 KB block of memory. Coarse page tables provide base addresses for either small or large pages. Large page descriptors must be repeated in 16 consecutive entries. Small page descriptors must be repeated in each consecutive entry.
Page 116: Translation Sequence For Large
If the large page descriptor is included in a fine page table, the high-order six bits of the page index and low-order six bits of the fine page table overlap. Each fine page table entry for a large page must be duplicated 64 times. Hardware Reference NS9215 20 19 Table index...
Page 117: Translating Sequence For Small
Translating sequence for small page references If a small page descriptor is included in a fine page table, the upper two bits of the page index and low-order two bits of the fine page table index overlap. Each fine page table entry for a small page must be duplicated four times. www.digiembedded.com Table index Translation table base...
Page 118: Translation Sequence For Tiny
TLB. For example, a 16 KB (large page) subpage entry is written into the TLB if the subpage permission differs, and a 64 KB entry is put in the TLB if the subpage permissions are identical. Hardware Reference NS9215 Table index Translation table base...
Page 119: Mmu Faults And Cpu Aborts
When you use subpage permissions and the page entry has to be invalidated, you must invalidate all four subpages separately. M M U f a u l t s a n d C P U a b o r t s .
Page 120: Priority Encoding Table
1 KB boundary. FAR values for Domain multi-word transfers Alignment External abort on translation Translation Hardware Reference NS9215 Source Size Alignment External abort on transmission First level Second level Translation Section page...
Page 121: Compatibility Issues
Domain Domain Permission External about for noncached reads, or nonbuffered writes To enable code to be ported easily to future architectures, it is recommended Compatibility that no reliance is made on external abort behavior. issues The Instruction Fault Status register is intended for debugging purposes only. D o m a i n a c c e s s c o n t r o l .
Page 122: User Permissions
................. . The sequence the MMU uses to check for access faults is different for sections and pages. The next figure shows the sequence for both types of access. Hardware Reference NS9215 Privileged permissions No access...
Page 123: Alignment Faults
Section translation Invalid fault Section No access (00) domain Reserved (10) fault Section permission Violation fault The conditions that generate each of the faults are discussed in the following sections. If alignment fault checking is enabled (the A bit in the R1: Control register is set; Alignment faults see "R1: Control register,"...
Page 124: Translation Faults
1 KB of the page. For large pages, AP3 is selected by the top 16 KB of the page and AP0 is selected by the bottom 16 KB of the page. The selected AP bits are then Hardware Reference NS9215...
Page 125: External Aborts
interpreted in the same way as for a section (see “Interpreting access permission bits” on page 121). The only difference is that the fault generated is a page permission fault. Tiny page: If the level one descriptor defines a page-mapped access and the level two descriptor is for a tiny page, the AP bits of the level one descriptor define whether the access is allowed in the same way as for a section.
Page 126: Disabling The Mmu
MVA-based TLB invalidate operation. The structure of the set-associative part of the TLB does not form part of the programmer’s model for the ARM926EJ-S processor. No assumptions must be made Hardware Reference NS9215 ). If this happens, enabling the MMU can be VA=MVA=PA ;...
Page 127: Caches And Write Buffer
about the structure, replacement algorithm, or persistence of entries in the set-associative part — specifically: Any entry written into the set-associative part of the TLB can be removed at any time. The set-associative part of the TLB must be considered as a temporary cache of translation/page table information.
Page 128: Write Buffer
Enabling the disabled. The caches are not accessed for reads or writes. The caches are enabled caches using the I, C, and M bits from the R1: Control register, and can be enabled independently of one another. Hardware Reference NS9215...
Page 129: Icache I And M Bit Settings
This table gives the I and M bit settings for the ICache, and the associated behavior. ICache I and M bit settings R1 I bit This table shows the page table C bit settings for the ICache (R1 I bit = M bit = 1). ICache page table C bit settings Page table C...
Page 130: Cache Mva And Set/Way Formats
This section shows how the MVA and set/way formats of ARM926EJ-S caches map to a generic virtually indexed, virtually addressed cache, shown next. The next figure shows a generic, virtually indexed, virtually addressed cache. Hardware Reference NS9215 Description ARM926EJ-S behavior Noncachable, DCache disabled.
Page 131: Generic, Virtually Indexed, Virtually Addressed Cache
Generic, virtually indexed, virtually addressed cache www.digiembedded.com Index Word Byte WO R K I N G W I T H T H E C P U Cache MVA and Set/Way formats Read data...
Page 132: Arm926Ej-S Cache Format
This table shows values of S and NSETS for an ARM926EJ-S cache. ARM926EJ-S 4 KB 8 KB 16 KB 32 KB 64 KB 128 KB Set/way/word format for 32-A ARM926EJ-S 31-A caches Hardware Reference NS9215 NSETS 1024 Index Word Byte S+5 S+4 Set select Word (= Index)
Page 133: Noncachable Instruction Fetches
In this figure: For example, with a 4-way cache A = 2: N o n c a c h a b l e i n s t r u c t i o n f e t c h e s .
Page 134: Ahb Behavior
The process of synchronizing instructions and data in level two memory must be invoked using some form of fully blocking operation, to ensure that the end of the operation can be determined using software. It is Hardware Reference NS9215...
Page 135: Sample Imb Sequences
recommended that either a nonbuffered store ( Invalidate the cache. The ICache must be invalidated to remove any stale copies of instructions that are no longer valid. If the ICache is not being used, or the modified regions are not in cachable areas of memory, this step might not be required.
Page 136 WO R K I N G W I T H T H E C P U Noncachable instruction fetches Hardware Reference NS9215...
Page 137: System Control Module
System Control Module he System Control Module configures and oversees system operations for the processor, and defines both the AMBA High-speed Bus (AHB) arbiter system and system memory address space. The System Control Module uses the following to configure and maintain system Features operations: AHB arbiter system...
Page 138: System Bus Arbiter
On powerup, only the CPU is assigned to one of the channels with 100% bandwidth strength as the default setting. The arbiter evaluates the BRR at every bus clock until one or more bus requests How the bus are registered. arbiter works Hardware Reference NS9215...
Page 139: Ownership
The arbiter stops evaluating the BRR until a bus grant is issued for the previous evaluation cycle. The arbiter grants the bus to requesting channels, in a round-robin manner, at the rising clock edge of the last address issued for the current transaction (note that each transaction may have multiple transfers), when a SPLIT response is sampled by the arbiter, or when the bus is idling.
Page 140: Split Transfers
BRC0[23:16] = 8’b1_0_00_0001 BRC0[15:8] BRC0[7:0] BRC1[31:24] = 8’b1_0_00_0011 Hardware Reference NS9215 signal is issued by the slave indicating that the slave is ready to hsplit_x[15:0] = [(75MHz/2) / (4 clock cycles per access x 5 masters)] x 16 bytes = 60MB/master...
Page 141: Address Decoding
BRC1[23:16] = 8’b1_0_00_0000 BRC1[15:8] BRC1[7:0] BRC2[31:24] = 8’b0_0_00_0000 BRC2[23:16] = 8’b0_0_00_0000 BRC2[15:8] BRC2[7:0] BRC3[31:24] = 8’b0_0_00_0000 BRC3[23:16] = 8’b0_0_00_0000 BRC3[15:8] BRC[7:0] A d d r e s s d e c o d i n g ................. . A central address decoder provides a select signal —...
Page 142: Programmable Timers
When enabled, system software must write to the Software Watchdog Timer register before it expires. When the timer does timeout, the system is preconfigured to generate an IRQ, an FIQ, or a RESET to restart the entire system. Hardware Reference NS9215 Size System functions 256 MB...
Page 143: General Purpose Timers/Counters
G e n e r a l p u r p o s e t i m e r s / c o u n t e r s ................. . Ten 32-bit general purpose timers/counters (GPTC) provide programmable time intervals to the CPU when used as one or multiple timers.
Page 144: 16-Bit Mode Options
The basic PWM function is output through GPIO through functions labeled PWM Ch N. This diagram illustrates the basic PWM function: Functional block diagram pulse width control period control pwm out 0 Hardware Reference NS9215 pulse width control Timer/Counter 0 pwm out 0 PWM 0 period control Timer/Counter 1...
Page 145: Enhanced Pwm Function
E n h a n c e d P W M f u n c t i o n ................. . Timer counters 6–9 have additional features to add enhanced PWM functionality: High register —...
Page 146: How The Quadrature Decoder/Counter Works
Input signals Legend: Quadrature encoding truth NC — No change table CW — Clockwise CCW — Counter clockwise Err — Error Hardware Reference NS9215 Clockwise Counter Clockwise...
Page 147: Monitors How Far The Encoder Has Moved
The counter keeps a running count of how far the encoder has moved. Monitors how far the encoder has The decoder increments a 32-bit counter when a state change is found in the moved positive direction. The decoder decrements a 32-bit counter when a state change is found in the other direction.
Page 148: Interrupt Controller
IRQ or FIQ, and enable the level. Interrupt Vector Address register. Contains the address of the interrupt service routine. The next figure shows a 32-vector interrupt controller: 32-vector interrupt controller Hardware Reference NS9215...
Page 149: Irq Characteristics
Interrupt Source 0 Interrupt Source 1 Interrupt Source 31 Invert Interrupt Source ID Reg 0 Interrupt Source 0 Interrupt Source 1 Interrupt Source 31 Invert Interrupt Source ID Reg 1 Interrupt Source 0 Interrupt Source 1 Interrupt Source 31 Invert Interrupt Source ID Reg 31 The IRQ interrupts are enabled by the respective enabling bits.
Page 150 S Y S T E M C O N T R O L M O D U L E Interrupt controller The interrupt sources are assigned as shown: Interrupt ID Hardware Reference NS9215 Interrupt source Watchdog Timer AHB Bus Error...
Page 151: Vectored Interrupt Controller (Vic) Flow
V e c t o r e d i n t e r r u p t c o n t r o l l e r ( V I C ) f l o w ................. . This is how the VIC flow works: An interrupt occurs.
Page 152: Pll Configuration And Control System Block Diagram
This table shows how each bit configures the powerup settings. Configuring the powerup settings 0 = Use an external pulldown 1 = Use the internal pullup Hardware Reference NS9215 div by 2,4,8,16,32,64, (programmable) mux select default is AHB clock (CCSel = 0)
Page 153 Pin name gpio_a[3] gpio_a[2] gpio_a[0], addr[23] addr[19:9] addr[7] addr[6:5] addr[4:0] www.digiembedded.com S Y S T E M C O N T R O L M O D U L E Configuration bits Endian configuration Little endian Big endian Boot mode Boot from SDRAM using serial SPI EEPROM Boot from Flash ROM Flash/SPI configuration...
Page 154: System Configuration Registers
A090 0048 A090 004C A090 0050 A090 0054 A090 0058 A090 005C A090 0060 A090 0064 A090 0068 A090 006C A090 0070 Hardware Reference NS9215 [31:24] [23:16] [15:8] General Arbiter Control BRC0 BRC1 BRC2 BRC3 Reserved AHB Error Detect Status 1...
Page 155 Offset A090 0074 A090 0078 A090 007C A090 0080 A090 0084 A090 0088 A090 008C A090 0090 A090 0094 A090 0098 A090 009C A090 00A0 A090 00A4 A090 00A8 A090 00AC A090 00B0 A090 00B4 A090 00B8 A090 00BC A090 00C0 A090 00C4 A090 00C8 A090 00CC...
Page 156 A090 0160 A090 0164 A090 0168 A090 016C A090 0170 A090 0174 A090 0178 Hardware Reference NS9215 [31:24] [23:16] [15:8] Interrupt Vector Address Register Level 13 Interrupt Vector Address Register Level 14 Interrupt Vector Address Register Level 15 Interrupt Vector Address Register Level 16...
Page 157 Offset A090 017C A090 0180 A090 0184 A090 0188 A090 018C A090 0190 A090 0194 A090 0198 A090 019C A090 01A0 A090 01A4 A090 01A8 A090 01AC A090 01B0 A090 01B4 A090 01B8 – A090 01CC A090 01D0 A090 01D4 A090 01D8 A090 01DC A090 01E0...
Page 158: General Arbiter Control Register
................. . Addresses: A090 0004 / 0008 / 000C / 0010 The BRC[0:3] registers control the AHB arbiter bandwidth allocation scheme. Hardware Reference NS9215 [31:24] [23:16]...
Page 159: Channel Allocation
This is how the channels are assigned in the four registers: Channel allocation Register name BRC0 BRC1 BRC2 BRC3 Register This table shows the bit definition for each channel, using data bits [07:00] as the Register bit example. assignment Bits D05:04 D03:00 A H B E r r o r D e t e c t S t a t u s 1...
Page 160: Ahb Error Detect Status 2
AHB error is found. This register also records which error condition was triggered. Note that this value is not reset on powerup but is reset when the AHB Interrupt Clear bit is set in the AHB Error Monitoring Configuration register (*). Register Hardware Reference NS9215 EDSI EDSI Access...
Page 161: Ahb Error Monitoring Configuration Register
Register bit Bits assignment D31:20 D16:15 D13:10 D09:06 D05:03 D02:00 A H B E r r o r M o n i t o r i n g C o n f i g u r a t i o n r e g i s t e r .
Page 162: Timer Master Control Register
................. . Address: A090 0024 The Timer Master Control register resets and enables the timer in groups, which is useful when using the timers in PW applications. Register T7RSE T7LSE T7HSE T6RSE T6LSE Hardware Reference NS9215 Reserved Reserved Access Mnemonic Reset...
Page 163 Register bit Bits assignment D31:22 www.digiembedded.com Access Mnemonic Reset Reserved T9RSE T9LSE T9HSE T8RSE T8LSE T8HSE T7RSE T7LSE T7HSE T6RSE T6LSE T6HSE S Y S T E M C O N T R O L M O D U L E Timer Master Control register Description Timer 9 reload step enable...
Page 164: Timer 0-4 Control Registers
................. . Addresses: A090 0190 / 0194 / 0198 / 019C / 01A0 Hardware Reference NS9215 Access...
Page 165 Register Register bit Bits assignment D31:16 D14:12 D09:06 www.digiembedded.com Reserved Cap Comp Debug Int Clr Access Mnemonic Reset Reserved Cap Comp Debug Int Clr S Y S T E M C O N T R O L M O D U L E Timer 0–4 Control registers Timer Int Sel...
Page 166: Timer 5 Control Register
................. . Address: A090 01A4 Register Cap Comp Hardware Reference NS9215 Access Mnemonic Reset...
Page 167 Register bit Bits assignment D31:19 D17:16 D14:12 www.digiembedded.com Access Mnemonic Reset Reserved Rel mode Cap Comp Debug Int Clr S Y S T E M C O N T R O L M O D U L E Timer 5 Control register Description Reload mode Initializes the timer and the reload value at terminal...
Page 168: Timer 6-9 Control Registers
................. . Addresses: A090 01A8 / 01AC / 01B0 / 01B4 Hardware Reference NS9215 Access...
Page 169 Register Register bit Bits assignment D31:18 D17:16 D14:12 www.digiembedded.com Reserved Cap Comp Debug Int Clr Access Mnemonic Reset Reserved Cap Comp Debug Int Clr S Y S T E M C O N T R O L M O D U L E Timer 6–9 Control registers Timer Mode...
Page 170: Timer 6-9 High Registers
................. . Addresses: A090 0078 / 007C / 0080 / 0084 The Timer 6–9 High registers contains the high registers for the enhanced PWM features available in timers 6 through 9. Hardware Reference NS9215 Access Mnemonic Reset...
Page 171: Timer 6-9 Low Registers
Register Register bit Bits assignment D31:00 T i m e r 6 – 9 L o w r e g i s t e r s ................. . Addresses: A090 0088 / 008C / 0090 / 0094 The Timer 6–9 Low registers contain the low registers for the enhanced PWM features available in timers 6 through 9.
Page 172: Timer 6-9 High And Low Step Registers
................. . Addresses: A090 00A8 / 00AC / 00B0 / 00B4 The Timer 6–9 reload Step registers contain the reload step registers for the enhanced PWM features available in timers 6 through 9. Hardware Reference NS9215 Hi Step Lo Step Access...
Page 173: Timer 0-9 Reload Count And Compare Register
Register Register bit Bits assignment D31:16 D14:00 T i m e r 0 - 9 R e l o a d C o u n t a n d C o m p a r e r e g i s t e r .
Page 174: Timer 0-9 Read And Capture Register
The Timer 0 to 9 Read and Capture register reads the current state of each timer and capture register. Register Register bit Bits assignment D31:16 D15:00 Hardware Reference NS9215 Access Mnemonic Reset Description Comp Rel Cnt Timer Compare register or Timer Reload Bits 31:16 Count register An external toggle or pulse is generated each time the timer value matches this value.
Page 175: Interrupt Vector Address Register Level 31-0
I n t e r r u p t V e c t o r A d d r e s s R e g i s t e r L e v e l 3 1 – 0 ................. . Addresses: A090 00C4 (level 0) / 00C8 / 00CC / 00D0 / 00D4 / 00D8 / 00DC / 00E0 / 00E4 / 00E8 / 00EC / 00F0 / 00F4 / 00F8 / 00FC / 0100 / 0104 / 0108 / 010C / 0110 / 0114 / 0118 / 011C / 0120 / 0124 / 0128 / 012C / 0130 / 0134 / 0138 /...
Page 176: Isaddr Register
Immediately before the read to the ISADDR register, always perform an extra write or read to any other internal register to consume an extra clock cycle. Make sure that the extra access is not optimized away. Hardware Reference NS9215 [31:24] [23:16]...
Page 177: Interrupt Status Active
Register Register bit Bits assignment D31:00 I n t e r r u p t S t a t u s A c t i v e ................. . Address: A090 0168 The Interrupt Status Active register shows the current active interrupt request.
Page 178: Interrupt Status Raw
................. . Address: A090 0174 The Software Watchdog Configuration register configures the software watchdog timer operation. Register Hardware Reference NS9215 Interrupt status raw (ISRAW) Interrupt status raw (ISRAW) Access Mnemonic...
Page 179: Software Watchdog Timer
Register bit Bits assignment D31:09 D02:00 S o f t w a r e W a t c h d o g T i m e r ................. . Address: A090 0178 The Software Watchdog Timer register services the watchdog timer.
Page 180: Clock Configuration Register
................. . Address: A090 017C The Clock Configuration register enables and disables clocks to each module on the AHB bus. Register Reser DM A Hardware Reference NS9215 Watchdog Timer Watchdog Timer Access Mnemonic Reset Description...
Page 181: Register Bit Assignment
Register bit assignment Bits D31:29 D28:26 D24:18 www.digiembedded.com Access Mnemonic Reset 0x000 Max CSC 0x000 CCSel Reserved MCOut 1 MCOut 0 Reserved EXT DMA S Y S T E M C O N T R O L M O D U L E Clock Configuration register Description Clock scale control...
Page 182: Module Reset Register
................. . Address: A090 0180 Hardware Reference NS9215 Access...
Page 183 The Module Reset register resets each module on the AHB bus. Register RST STAT Reser DM A Register bit Bits assignment D31:29 D28:15 www.digiembedded.com Reser Reser Access Mnemonic Reset RST STAT Not reset Reserved EXT DMA IO hub Reserved Reserved S Y S T E M C O N T R O L M O D U L E Module Reset register Reserved...
Page 184: Miscellaneous System Configuration And Status Register
................. . Address: A090 0184 The Miscellaneous System Configuration and Status register configures miscellaneous system configuration bits. Register Hardware Reference NS9215 Access Mnemonic Reset Description...
Page 185 Indicates the hardware identification and revision of the processor chip. Identification Identifies the chip as: NS9750B-A1 NS9360 NS9210 NS9215 Auxiliary analog comparator status Level is below 2.4V Level is above 2.4V Boot mode Boot from SPI Boot from flash If boot mode is set to boot from flash:...
Page 186: Pll Configuration Register
RefClk / NR+1) PLL Vco Register Register bit assignment Bits D31:17 D16:08 D06:05 D04:00 Hardware Reference NS9215 PLL Vco = (RefClk / NR+1) * NF+1 ClkOut = PLL Vco / OD+1 range: 275KHz–550MHz range: 110MHz–550MHz Reserved Access Mnemonic Reset Description...
Page 187: Active Interrupt Level Id Status Register
A c t i v e I n t e r r u p t L e v e l I D S t a t u s r e g i s t e r ................. . Address: A090 018C The Active Interrupt Level ID Status register is six bits in length, and shows the current active interrupt level ID.
Page 188 S Y S T E M C O N T R O L M O D U L E Power Management Register bit Bits assignment D29:22 Hardware Reference NS9215 Access Mnemonic Reset Description Slp en Deprecated Chip sleep enable This control bit is provided for backwards...
Page 189 Bits D15:13 D10:06 www.digiembedded.com Access Mnemonic Reset WakeIntClr Ext Int 3 Ext Int 2 Ext Int 1 Ext Int 0 Reserved Reserved UART D UART C UART B S Y S T E M C O N T R O L M O D U L E Power Management Description CPU wake interrupt clear...
Page 190: Ahb Bus Activity Status
................. . Addresses: A090 01D0 / 01D4 Hardware Reference NS9215 Access...
Page 191: System Memory Chip Select 1 Dynamic Memory Base And Mask Registers
These control registers set the base and mask for system memory chip select 0, with a minimum size of 4K. The powerup default settings produce a memory range of 0x0000 0000 — 0x0FFF FFFF Registers Chip select 0 base (CS0B) Chip select 0 mask (CS0M) Register bit Bits...
Page 192: System Memory Chip Select 2 Dynamic Memory Base And Mask Registers
These control registers set the base and mask for system memory chip select 2, with a minimum size of 4K. The powerup default settings produce a memory range of 0x2000 0000 — 0x2FFF FFFF Hardware Reference NS9215 Chip select 1 base (CS1B) Chip select 1 mask (CS1M)
Page 193: System Memory Chip Select 3 Dynamic Memory Base And Mask Registers
Registers Chip select 2 base (CS2B) Chip select 2 mask (CS2M) Register bit Bits assignment D31:12 D11:00 D31:12 D11:01 S y s t e m M e m o r y C h i p S e l e c t 3 D y n a m i c M e m o r y B a s e a n d M a s k r e g i s t e r s .
Page 194: System Memory Chip Select 0 Static Memory Base And Mask Registers
These control registers set the base and mask for system memory chip select 0, with a minimum size of 4K. The powerup default settings produce a memory range of 0x4000 0000 — 0x4FFF FFFF Hardware Reference NS9215 Chip select 3 base (CS3B) Chip select 3 mask (CS3M)
Page 195: Register Bit Assignment
Registers Chip select 0 base (CS0B) Chip select 0 mask (CS0M) Register bit Bits assignment D31:12 D11:00 D31:12 D11:01 S y s t e m M e m o r y C h i p S e l e c t 1 S t a t i c M e m o r y B a s e a n d M a s k r e g i s t e r s .
Page 196: System Memory Chip Select 2 Static Memory Base And Mask Registers
These control registers set the base and mask for system memory chip select 2, with a minimum size of 4K. The powerup default settings produce a memory range of 0x6000 0000 — 0x6FFF FFFF Hardware Reference NS9215 Chip select 1 base (CS1B) Chip select 1 mask (CS1M)
Page 197: System Memory Chip Select 3 Static Memory Base And Mask Registers
Registers Chip select 2 base (CS2B) Chip select 2 mask (CS2M) Register bit Bits assignment D31:12 D11:00 D31:12 D11:01 S y s t e m M e m o r y C h i p S e l e c t 3 S t a t i c M e m o r y B a s e a n d M a s k r e g i s t e r s .
Page 198: Gen Id Register
................. . Address: A090 0210 This register is read-only, and indicates the state of addr[19:09] pins at powerup. Hardware Reference NS9215 Chip select 3 base (CS3B) Chip select 3 mask (CS3M)
Page 199: External Interrupt 0-3 Control Register
Register Register bit Bits assignment D31:11 D10:00 E x t e r n a l I n t e r r u p t 0 – 3 C o n t r o l r e g i s t e r .
Page 200: Rtc Module Control Register
The RTC Module Control register controls the RTC module. Register Register bit Bits Access assignment D31:05 Hardware Reference NS9215 Mnemonic Reset Description PLTY Polarity If level-sensitive, the input source is active high. If edge-sensitive, generate an interrupt on the rising edge of the external interrupt.
Page 201 Bits www.digiembedded.com Access Mnemonic Reset Rdy int Int stat Standby mode Clk rdy int S Y S T E M C O N T R O L M O D U L E RTC Module Control register Description RTC clock ready interrupt status RTC clock ready interrupt not asserted RTC clock ready interrupt asserted Note:...
Page 202 S Y S T E M C O N T R O L M O D U L E RTC Module Control register Hardware Reference NS9215...
Page 203: Memory Controller
Memory Controller he Multiport Memory Controller is an AMBA-compliant system-on-chip (SoC) peripheral that connects to the Advanced High-performance Bus (AHB). The remainder of this chapter refers to this controller as the memory controller. The memory controller provides these features: Features AMBA 32-bit AHB compliancy Dynamic memory interface support including SDRAM and JEDEC low-power SDRAM...
Page 204: Low-Power Operation
Partial array refresh can be programmed by initializing the SDRAM memory device SDRAM partial array refresh appropriately. When the memory device is put into self-refresh mode, only the memory banks specified are refreshed. The memory banks that are not refreshed lose their data contents. Hardware Reference NS9215 clk_en...
Page 205: Memory Map
M e m o r y m a p ................. . The memory controller provides hardware support for booting from external nonvolatile memory.
Page 206: Example: Boot From Flash, Sdram Remapped After Boot
This is the boot sequence: At power-on, the reset chip select 1 is mirrored into chip select 4 (and chip select 0). Hardware Reference NS9215 ) goes inactive, the processor starts booting reset_n in memory. 0x00000000. after...
Page 207: Static Memory Controller
When the power-on reset ( from The software programs the optimum delay values in flash memory so the boot code can run at full speed. The code branches to chip select 1 so the code can continue executing from the non-remapped memory location.
Page 208: Extended Wait Transfers
Using extremely long transfer times might mean that SDRAM devices are not refreshed correctly. Very slow transfers can degrade system performance, as the external memory interface is tied up for long periods of time. This has detrimental effects on Hardware Reference NS9215 signal. This allows a slow peripheral with ns_ta_strb ns_ta_strb ns_ta_strb signal is valid only when the EW bit is enabled.
Page 209: Memory Mapped Peripherals
time critical services, such as interrupt latency and low latency devices; for example, video controllers. Some systems use external peripherals that can be accessed using the static Memory mapped memory interface. Because of the way many of these peripherals function, the read peripherals and write transfers to them must not be buffered.
Page 210: Programmable Enable
Static Memory Read Delay register. The WAITTURN field in the Static Memory Turn Round Delay register determines the number of bus turnaround wait states added between external read and write transfers. Hardware Reference NS9215 ) and memory address ( cs_n addr[27:0] ).
Page 211: Static Memory Read: Timing And Parameters
S t a t i c m e m o r y r e a d : T i m i n g a n d p a r a m e t e r s ................. . This section shows static memory read timing diagrams and parameters.
Page 212: External Memory Read Transfer With Two Output Enable Delay States
All transfers are treated as separate reads, so have the minimum of five AHB cycles added. clk_out addr data cs[n] st_oe_n Hardware Reference NS9215 Value ). Seven AHB cycles are required for the transfer, five for the D(A) Value D(A) D(B)
Page 213: Burst Of Zero Wait States With Fixed Length
Timing parameter WAITRD WAITOEN WAITPAGE WAITWR WAITWEN WAITTURN This diagram shows a burst of zero wait state reads with the length specified. Burst of zero wait Because the length of the burst is known, the chip select can be held asserted states with fixed length during the whole burst and generate the external transfers before the current AHB...
Page 214: Asynchronous Page Mode Read
(plus three wait states); the following (up to 3) sequential transfers have only one AHB wait state. This gives increased performance over the equivalent nonpage mode ROM timing. Hardware Reference NS9215 D(A) D(A+4) Value cycles.
Page 215: External Memory 32-Bit Burst Read From 8-Bit Memory
clk_out addr data cs[n] st_oe_n Timing parameter WAITRD WAITOEN WAITPAGE WAITWR WAITWEN WAITTURN This diagram shows a 32-bit read from an 8-bit page mode ROM device, causing four External memory burst reads to be performed. A total of eight AHB wait states are added during this 32-bit burst read from 8-bit transfer, five AHB arbitration cycles and then one for each of the subsequent reads.
Page 216: Static Memory Write Control
Hardware Reference NS9215 WAITWEN ) and address signals ( ). The write access time is determined addr[27:0]_n field in the bank control register (see “StaticMemory Turn WAITTURN ). One wait state is added.
Page 217: External Memory Write Transfer With Two Wait States
Timing parameters WAITRD WAITOEN WAITPAGE WAITWR WAITWEN WAITTURN This diagram shows a single external memory write transfer with two wait states External memory write transfer WAITWR=2 with two wait states clk_out addr data cs{n} st_we_n Timing parameter WAITRD WAITOEN WAITPAGE WAITWR WAITWEN WAITTURN...
Page 218: Two External Memory Write Transfers With Zero Wait States
Timing parameter WAITRD WAITOEN WAITPAGE WAITWR WAITWEN WAITTURN Write timing for flash memory is the same as for SRAM devices. Flash memory Hardware Reference NS9215 Value . The maximum speed of write transfers is HBURST D(A) D(A+4) Value...
Page 219: Bus Turnaround
B u s t u r n a r o u n d ................. . The memory controller can be configured for each memory bank to use external bus turnaround cycles between read and write memory accesses.
Page 220: Write Followed By A Read With No Turnaround
(as for any read-write transfer sequence). clk_out addr data st_oe_n cs[n] st_we_n Hardware Reference NS9215 D(A) D(B) Value D(A) D(B)
Page 221: Byte Lane Control
Timing parameters WAITRD WAITOEN WAITPAGE WAITWR WAITWEN WAITTURN B y t e l a n e c o n t r o l ................. . The memory controller generates the byte lane control signals according to these attributes: Little or big endian operation...
Page 222: Address Connectivity
A[20:0] CE_n OE_n data_mask[3] WE_n data[31:24] IO[7:0] 16-bit bank consisting of two 8-bit devices Hardware Reference NS9215 data_mask ) inputs of each 8-bit memory. The WE_n data_mask[3:0] signals are deasserted high, enabling the data_mask[3:0] A[20:0] CE_n OE_n data_mask[2]...
Page 223: Memory Banks Constructed From 16-Or 32-Bit Memory Devices
For memory banks constructed from 16- or 32-bit memory devices, it is important Memory banks that the byte lane select (PB) bit is set to 1 within the respective memory bank constructed from 16-or 32-bit control register. This asserts all memory devices during a read, all device bytes must be selected to avoid undriven byte lanes on the read data value.
Page 224 M E M O R Y C O N T R O L L E R Address connectivity addr[22:0] cs[0] st_oe_n cs[1] st_we_n cs[2] data_mask[3] data_mask[2] data_mask[1] data_mask[0] Hardware Reference NS9215 addr[22:2] datat[31:0] A[20:0] Q[31:0] CE_n OE_n 2Mx32 ROM addr[11:2] data[31:16] A[15:0] IO[15:0]...
Page 225: Dynamic Memory Controller
D y n a m i c m e m o r y c o n t r o l l e r ................. . Each dynamic memory chip select can be configured for write-protection by setting Write protection the appropriate bit in the write protect (P) field on the Dynamic Memory...
Page 226: Left-Shift Value Table: 32-Bit Wide Data Bus Sdram (Rbc)
The SDRAM is now ready for normal operation. Left-shift value Device size table: 32-bit wide data bus SDRAM (RBC) 128M Hardware Reference NS9215 value in the Dynamic Control register to 01 — Issue SDRAM SDRAMInit Parameter Parameter description Burst length Burst type...
Page 227: Left-Shift Value Table: 32-Bit Wide Data Bus Sdram (Brc)
Device size 256M 512M Left-shift value Device size table: 32-bit wide data bus SDRAM (BRC) 128M 256M 512M Left-shift value Device size table: 16-bit wide data bus SDRAM (RBC) 256M 512M www.digiembedded.com Configuration Load Mode register left shift 1 x 8M x 32 2 x 16M x 16 4 x 32M x 8 2 x 32M x 16...
Page 228: Left-Shift Value Table: 16-Bit Wide Data Bus Sdram (Brc)
Hardware Reference NS9215 Configuration Load Mode register left shift 1 x 1M x 16 2 x 2M x 8 1 x 4M x 16 2 x 8M x 8 1 x 8M x 16...
Page 229: 32-Bit Wide Configuration
Signal addr[14] addr[15] addr[16] addr[17] addr[18] addr[19] addr[20] addr[21] addr[22] addr[23] ap10 data[31:0] * A12 used only in 4 x 16M x 8 configurations 32-bit wide Signal configuration addr[1] addr[2] addr[3] addr[4] addr[5] addr[6] addr[7] addr[8] addr[9] addr[10] addr[11] addr[12] addr[13] addr[14] www.digiembedded.com...
Page 230: Registers
Address A070 0000 A070 0004 A070 0008 A070 0020 A070 0024 A070 0028 A070 0030 A070 0034 A070 0038 A070 003C A070 0040 Hardware Reference NS9215 16M device 64M device 128M SDRAM SDRAM device signal signal SDRAM signal A10/AP A10/AP...
Page 231 Address A070 0044 A070 0048 A070 004C A070 0050 A070 0054 A070 0058 A070 0080 A070 0100 A070 0104 A070 0120 A070 0124 A070 0140 A070 0144 A070 0160 A070 0164 A070 0200 A070 0204 A070 0208 A070 020C A070 0210 A070 0214 A070 0218 A070 0220...
Page 232: Reset Values
................. . Address: A070 0000 The Control register controls the memory controller operation. The control bits can be changed during normal operation. Register Hardware Reference NS9215 Register Description StaticConfig2 Static Memory Configuration Register 2...
Page 233 Register bit Bits assignment D31:03 www.digiembedded.com Access Mnemonic Description Reserved N/A (do not modify) Low-power mode Normal mode (reset value on Low-power mode Indicates normal or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit or by power- on reset.
Page 234: Status Register
The Configuration register configures memory controller operation. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. Hardware Reference NS9215 Reserved Reserved Mnemonic...
Page 235: Dynamic Memory Control Register
Register Register bit Bits assignment D31:01 D y n a m i c M e m o r y C o n t r o l r e g i s t e r ................. . Address: A070 0020 The Dynamic Memory Control register controls dynamic memory operation.
Page 236: Dynamic Memory Refresh Timer Register
................. . Address: A070 0024 Hardware Reference NS9215 Mnemonic...
Page 237: Register
The Dynamic Memory Refresh Timer register configures dynamic memory operation. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.These bits can, however, be changed during normal operation if necessary.
Page 238: Dynamic Memory Precharge Command Period Register
This value normally is found in SDRAM datasheets as t The Dynamic Memory Precharge Command Period register is used for all four Note: dynamic memory chip selects. The worst case value for all chip selects must be programmed. Register Hardware Reference NS9215 Reserved Reserved Mnemonic Description Reserved...
Page 239: Dynamic Memory Active To Precharge Command Period Register
Register bit Bits assignment D31:04 D03:00 D y n a m i c M e m o r y A c t i v e t o P r e c h a r g e C o m m a n d P e r i o d r e g i s t e r .
Page 240: Dynamic Memory Self-Refresh Exit Time Register
The Dynamic Memory Last Data Out to Active Time register is used for all four Note: dynamic memory chip selects. The worst case value for all chip selects must be programmed. Hardware Reference NS9215 . It is recommended that this register be modified during SREX Reserved...
Page 241: Dynamic Memory Data-In To Active Command Time Register
Register Register bit Bits assignment D31:04 D03:00 D y n a m i c M e m o r y D a t a - i n t o A c t i v e C o m m a n d T i m e r e g i s t e r .
Page 242: Dynamic Memory Write Recovery Time Register
Register Register bit Bits Access assignment D31:04 D03:00 Hardware Reference NS9215 Mnemonic Description Reserved N/A (do not modify) Data-in to active command (t 0x0–0xE n+1 clock cycles, where the delay is in 15 clock cycles (reset value on .
Page 243: Dynamic Memory Active To Active Command Period Register
D y n a m i c M e m o r y A c t i v e t o A c t i v e C o m m a n d P e r i o d r e g i s t e r .
Page 244: Dynamic Memory Exit Self-Refresh Register
This value normally is found in SDRAM datasheets as t The Dynamic Memory Exit Self-refresh register is used for all four dynamic Note: memory chip selects. The worst case value for all the chip selects must be programmed. Hardware Reference NS9215 Reserved Reserved Mnemonic Description...
Page 245: Dynamic Memory Active Bank A To Active Bank B Time Register
Register Register bit Bits assignment D31:05 D04:00 D y n a m i c M e m o r y A c t i v e B a n k A t o A c t i v e B a n k B T i m e r e g i s t e r .
Page 246: Dynamic Memory Load Mode Register To Active Command Time Register
Register Register bit Bits Access assignment D31:045 D03:00 Hardware Reference NS9215 Mnemonic Description Reserved N/A (do not modify) Active Bank A to Active Bank B 0x0–0xE n+1 clock cycles, where the delay is in 16 clock cycles (reset on...
Page 247: Static Memory Extended Wait Register
S t a t i c M e m o r y E x t e n d e d W a i t r e g i s t e r ................. . Address: A070 0080 The Static Memory Extended Wait register times long static memory read and write transfers (which are longer than can be supported by the Static Memory Read Delay...
Page 248 Register Rsvd Register bit Bits Access assignment D31:21 D18:15 D12:07 D06:05 D04:03 D02:00 Hardware Reference NS9215 Reserved Rsvd Mnemonic Description Reserved N/A (do not modify) Protect Write protect Writes not protected (reset value on Write protected BDMC Buffer enable...
Page 249: Address Mapping For The Dynamic Memory Configuration Registers
The next table shows address mapping for the Dynamic Memory Configuration 0-3 Address mapping registers. Address mappings that are not shown in the table are reserved. for the Dynamic Memory Configuration [14] [12] registers 16-bit external bus high-performance address mapping (row, bank column) 16-bit external bus low-power SDRAM address mapping (bank, row, column) 32-bit extended bus high-performance address mapping (row, bank, column) www.digiembedded.com...
Page 250: Chip Select And Memory Devices
................. . Address: A070 0104 / 0124 / 0144 / 0164 Hardware Reference NS9215 [11:9]...
Page 251: Staticmemory Configuration 0-3 Registers
The Dynamic Memory RAS and CAS Delay 0–3 registers allow you to program the RAS and CAS latencies for the relevant dynamic memory. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions.
Page 252 M E M O R Y C O N T R O L L E R StaticMemory Configuration 0–3 registers Register Register bit Bits Access assignment D31:21 D18:09 Hardware Reference NS9215 Reserved Reserved Mnemonic Description Reserved N/A (do not modify) PSMC Write protect...
Page 253 Bits D05:04 www.digiembedded.com Access Mnemonic Description Byte lane state For reads, all bits in For writes, the respective active bits in (reset value for chip select 0, 2, and 3 on For reads, the respective active bits in For writes, the respective active bits in Note: Setting this bit to 0 disables the write enable signal.
Page 254: Staticmemory Write Enable Delay 0-3 Registers
It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low- power or disabled mode. Register Hardware Reference NS9215 Mnemonic Description BMODE Burst mode Allows the static output enable signal to toggle during bursts.
Page 255: Static Memory Output Enable Delay 0-3 Registers
Register bit Bits assignment D31:04 D03:00 S t a t i c M e m o r y O u t p u t E n a b l e D e l a y 0 – 3 r e g i s t e r s .
Page 256: Static Memory Read Delay 0-3 Registers
The Static Memory Page Mode Read Delay 0–3 registers allow you to program the delay for asynchronous page mode sequential accesses. These registers control the overall period for the read cycle. It is recommended that these registers be Hardware Reference NS9215 Reserved Reserved...
Page 257: Register Bit Assignment
modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. Register Register bit Bits assignment D31:05 D04:00 S t a t i c M e m o r y W r i t e D e l a y 0 – 3 r e g i s t e r s .
Page 258: Staticmemory Turn Round Delay 0-3 Registers
It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. Register Hardware Reference NS9215 Reserved Reserved Mnemonic...
Page 259 Register bit Bits assignment D31:04 D03:00 To prevent bus contention on the external memory databus, the WAITTURN field controls the number of bus turnaround cycles added between static memory read and write accesses. The WAITTURN field also controls the number of turnaround cycles between static memory and dynamic memory accesses.
Page 260 M E M O R Y C O N T R O L L E R StaticMemory Turn Round Delay 0–3 registers Hardware Reference NS9215...
Page 261: Features
Ethernet Communication Module he Ethernet Communication module consists of an Ethernet Media Access Controller (MAC) and Ethernet front-end module. The Ethernet MAC interfaces to an external PHY through the industry-standard interface: Media Independent Interface (MII). The Ethernet front-end module provides all of the control functions to the MAC.
Page 262: Ethernet Communications Module
................. . The Ethernet MAC includes a full function 10/100 Mbps Media Access Controller (MAC), station address filtering logic (SAL), statistic collection module (STAT), and MII. Hardware Reference NS9215 Ethernet PHY MGMT Ethernet...
Page 263: Mac Module Block Diagram
MAC module block diagram MAC module Feature features MAC Core HOST CLK & Reset MIIM STAT www.digiembedded.com E T H E R N E T C O M M U N I C A T I O N M O D U L E Description 10/100 megabit Media Access Controller Performs the CSMA/CD function.
Page 264: Phy Interface Mappings
................. . The station address logic module examines the destination address field of incoming frames, and filters the frames before they are stored in the Ethernet front-end Hardware Reference NS9215 Description Station address logic Performs destination address filtering.
Page 265: Mac Receiver
module. The filtering options, listed next, are programmed in the Station Address Filter register (see page 301). Accept frames to destination address programmed in the SA1, SA2, and SA3 registers (Station Address registers, beginning on page 300) Accept all frames Accept all multicast frames Accept all multicast frames using HT1 and HT2 registers.
Page 266: Ethernet Front-End Module
Ethernet MAC and commits them to external system processor memory. Bad frames (for example, invalid checksum or code violation) and frames with unacceptable destination addresses are discarded. Hardware Reference NS9215 To Receive/Transmit Packet Processors Control Registers...
Page 267: Transmit Packet Processor
The 2K byte RX_FIFO allows the entire Ethernet frame to be buffered while the receive byte count is analyzed. The receive byte count is analyzed by the receive packet processor to select the optimum-sized buffer for transferring the received frame to system memory. The processor can use one of four different-sized receive buffers in system memory.
Page 268: Transferring A Frame To System Memory
Ethernet General Status register. At the end of a frame, the next buffer descriptor for the ring just used is read from system memory and stored in the registers internal to the Hardware Reference NS9215 logic manages the transfer of a frame in the RX_FIFO to system memory. ERXDMA logic that a good frame is in the receive FIFO.
Page 269: Receive Buffer Descriptor Field Definitions
Receive buffer Field descriptor field definitions Buffer pointer Status Buffer length T r a n s m i t p a c k e t p r o c e s s o r ................. . Transmit frames are transferred from system memory to the transmit packet processor into a 256-byte TX_FIFO.
Page 270: Transmit Buffer Descriptor Format
OFFSET + 8 OFFSET + C Transmit buffer Field descriptor field definitions Buffer pointer Status Hardware Reference NS9215 30 29 28 Source Address Buffer Length (11-bits used) Destination Address (not used) Reserved Description bit, which, when set, tells the WRAP TX_WR within the continuous list of descriptors in the TX buffer descriptor RAM.
Page 271: Transmitting A Frame
Field Buffer length Setting the EXTDMA (enable transmit DMA) bit in Ethernet General Control Register Transmitting a #1 starts the transfer of transmit frames from the system memory to the TX_FIFO. frame TX_WR If the F bit is set, it transfers data from system memory to the TX_FIFO using the buffer pointer as the starting point.
Page 272: Frame Transmitted Successfully
Ethernet underrun – Insufficient bandwidth is assigned to the Ethernet transmitter. Hardware Reference NS9215 logic examines the status received from the MAC after it has transmitted logic has no frame to transmit) bit in the Ethernet Interrupt TX_WR logic detects that the frame was aborted or had an error, the logic...
Page 273: Ethernet Slave Interface
– When an underrun occurs, it is also possible for the Ethernet transmitter to send out a corrupted packet with a good Ethernet CRC if the MAC is configured to add the CRC to the frame (that is, CRCEN in MAC Configuration Register #2 is set to 1). E t h e r n e t s l a v e i n t e r f a c e .
Page 274: Status Bits
MAC_HRST SRST RPERFUN RPEMCST Hardware Reference NS9215 Description No buffer is available for this frame because all 4 buffer rings are disabled, full, or no available buffer is big enough for the frame. No buffer is available for this frame because all 4 buffers are disabled or full.
Page 275: Multicast Address Filtering
Bit field RPETFUN MIIM M u l t i c a s t a d d r e s s f i l t e r i n g ................. . The RX-WR logic contains a programmable 8-entry multicast address filter that provides more restrictive filtering than that available in the MAC using the SAL.
Page 276: Multicast Address Filtering Example 2
Set the enable bit for the address filter that was just changed. If the address filters are changed only when the processing frames, as recommended, the address filter registers can be updated without using this procedure. Hardware Reference NS9215 Value Function 0x10...
Page 277: Ethernet Control And Status Registers
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s ................. . All configuration registers must be accessed as 32-bit words and as single accesses only.
Page 278 A060 0A6C A060 0A70 A060 0A74 A060 0A78 A060 0A7C A060 0A80 A060 0A84 A060 0A88 A060 0A8C Hardware Reference NS9215 Register Description RXDPTR RX_D Buffer Descriptor Pointer register EINTR Ethernet Interrupt Status register EINTREN Ethernet Interrupt Enable register TXPTR...
Page 279: Ethernet General Control Register #1
Address A060 0A90 A060 0A94 A060 0A98 A060 0A9C A060 0AA0 A060 0AA4 A060 0AA8 A060 0AAC A060 0AB0 A060 0AB4 A060 0AB8 A060 0ABC A060 0AC0 A060 1000 A060 2000 E t h e r n e t G e n e r a l C o n t r o l R e g i s t e r # 1 .
Page 280 E T H E R N E T C O M M U N I C A T I O N M O D U L E Ethernet General Control Register #1 Register bit Bits assignment D27:24 Hardware Reference NS9215 Access Mnemonic Reset Description Enable RX packet processing...
Page 281 Bits D18:13 www.digiembedded.com E T H E R N E T C O M M U N I C A T I O N M O D U L E Access Mnemonic Reset Description ETXDMA Enable transmit DMA Must be set active high to allow the transmit packet processor to issue transmit data requests to the AHB interface.
Page 282: Ethernet General Control Register #2
................. . Address: A060 0004 Register Hardware Reference NS9215 Access Mnemonic...
Page 283: Register Bit Assignment
Register bit Bits assignment D31:08 D06:04 E t h e r n e t G e n e r a l S t a t u s r e g i s t e r ................. . Address: A060 0008 www.digiembedded.com E T H E R N E T C O M M U N I C A T I O N M O D U L E...
Page 284: Ethernet Transmit Status Register
Ethernet Transmit Status register is loaded at the same time. Bits [15:0] are also loaded into the Status field of the last transmit buffer descriptor for the frame. Register Hardware Reference NS9215 Reserved Reserved Mnemonic...
Page 285 Register bit Bits assignment D31:16 www.digiembedded.com E T H E R N E T C O M M U N I C A T I O N M O D U L E Access Mnemonic Reset Description Reserved TXOK Frame transmitted OK When set, indicates that the frame has been delivered to and emptied from the transmit FIFO without problems.
Page 286: Ethernet Receive Status Register
Ethernet Receive Status register is loaded at the same time. Bits [15:0] are also loaded into the status field of the receive buffer descriptor used for the frame. Hardware Reference NS9215 Mnemonic Reset...
Page 287 Register RXCE RXDV Register bit Bits assignment D31:27 D26:16 D08:07 www.digiembedded.com E T H E R N E T C O M M U N I C A T I O N M O D U L E Reserved RXOK RXBR RXMC Rsvd...
Page 288: Mac Configuration Register #1
Register bit Bits Access assignment D31:16 D13:12 D07:05 Hardware Reference NS9215 Mnemonic Reset Description RXSHT Receive frame is too short Set when the frame’s length is less than 64 bytes. Short frames are accepted only when the ERXSHT bit is set to 1 in Ethernet General Control Register #1.
Page 289: Mac Configuration Register #2
Bits D03:01 M A C C o n f i g u r a t i o n R e g i s t e r # 2 ................. . Address: A060 0404 MAC Configuration Register #2 provides additional bits that control functionality within the Ethernet MAC block.
Page 290 E T H E R N E T C O M M U N I C A T I O N M O D U L E MAC Configuration Register #2 Bits Access Hardware Reference NS9215 Mnemonic Reset Definition LONGP Long preamble enforcement Allows any length preamble (as defined in the 802.3u...
Page 291: Pad Operation Table For Transmit Frames
Bits PAD operation Type AUTOP table for transmit frames B a c k - t o - B a c k I n t e r - P a c k e t - G a p r e g i s t e r .
Page 292: Non Back-To-Back Inter-Packet-Gap Register
................. . Address: A060 040C Register Rsvd Hardware Reference NS9215 Mnemonic Reset Description...
Page 293: Collision Window/Retry Register
Register bit assignment Bits D31:15 D14:08 D06:00 C o l l i s i o n W i n d o w / R e t r y r e g i s t e r ................. . Address: A060 0410 Register Reserved...
Page 294: Maximum Frame Register
................. . Address: A060 0414 Register Hardware Reference NS9215 Mnemonic Reset...
Page 295: Mii Management Configuration Register
Register bit Bits assignment D31:16 D15:00 M I I M a n a g e m e n t C o n f i g u r a t i o n r e g i s t e r .
Page 296: Clocks Field Settings
................. . Address: A060 0424 Hardware Reference NS9215 Mnemonic...
Page 297: Mii Management Address Register
Register If both SCAN and READ are set, SCAN takes precedence. Register bit Note: assignment Bits D31:02 M I I M a n a g e m e n t A d d r e s s r e g i s t e r .
Page 298: Mii Management Write Data Register
................. . Address: A060 0430 Hardware Reference NS9215 Mnemonic...
Page 299: Mii Management Indicators Register
Register Register bit Bits assignment D31:16 D15:00 M I I M a n a g e m e n t I n d i c a t o r s r e g i s t e r ................. . Address: A060 0434 Register Register bit...
Page 300: Station Address Registers
The 48-bit station address is loaded into Station Address Register #1, Station Address Register #2, and Station Address Register #3, for use by the station address logic (see “Station address logic (SAL)” on page 264). Registers Hardware Reference NS9215 Mnemonic Reset Description...
Page 301: Station Address Filter Register
Register bit Bits assignments for all three registers Station Address Register #1 D31:16 D15:08 D07:00 Station Address Register #2 D31:16 D15:08 D07:00 Station Address Register #3 D31:16 D15:08 D07:00 Octet #6 is the first byte of a frame received from the MAC. Octet #1 is the Note: last byte of the station address received from the MAC.
Page 302: Registerhash Tables
HT1 stores enables for the lower 32 CRC addresses; HT2 stores enables for the upper 32 CRC addresses. Address: A060 0504 Register bit assignment Bits Access D31:00 Hardware Reference NS9215 Reserved Reserved Mnemonic Reset Description Reserved Enable promiscuous mode; receive all frames...
Page 303: Ht2
Address: A060 0508 Register bit assignment Bits D31:00 S t a t i s t i c s r e g i s t e r s ................. . Address: A060 0680 (base register) The Statistics module has 39 counters and 4 support registers that count and save Ethernet statistics.
Page 304: Receive Statistics Counters Address Map
D23:00 Incremented for each received frame (including bad packets, and all unicast, Receive packet broadcast, and multicast packets). counter (A060 06A0) D31:18 Hardware Reference NS9215 Register Transmit and receive counters TRMAX Transmit & receive 1024 TRMGV Transmit & receive 1519...
Page 305: Receive Fcs Error Counter (A060 06A4)
D17:00 Incremented for each frame received with a length of 64 to 1518 bytes, and Receive FCS error containing a frame check sequence (FCS) error. FCS errors are not counted for VLAN counter (A060 06A4) frames that exceed 1518 bytes or for any frames with dribble bits. D31:12 D11:00 Incremented for each good multicast frame with a length no greater than 1518...
Page 306: Receive Alignment Error Counter (A060 06Bc)
Incremented for each frame received that is less than 64 bytes in length and Receive fragments contains an invalid FCS; this includes integral and non-integral lengths. counter (A060 06D4) D31:12 D11:00 Hardware Reference NS9215 Reset = Read as 0 Reserved Reset = 0x000 RALN Reset = Read as 0 Reserved...
Page 307: Receive Jabber Counter (A060 06D8)
Incremented for frames received that exceed 1518 bytes (non-VLAN) or 1522 bytes Receive jabber (VLAN) and contain an invalid FCS, including alignment errors. This counter does not counter (A060 06D8) increment when a packet is truncated to 1518 (non-VLAN) or 1522 (VLAN) bytes by MAXF.
Page 308: Transmit Packet Counter (A060 06E4)
Incremented for each frame transmitted that experienced exactly one collision Transmit single during transmission. collision packet counter (A060 06FC) D31:12 D11:00 Hardware Reference NS9215 Reset = Read as 0 Reserved Reset = 0x00000 TPKT Reset = Read as 0 Reserved Reset = 0x00000...
Page 309: Transmit Multiple Collision Packet Counter (A060 0700)
Incremented for each frame transmitted that experienced 2–15 collisions (including Transmit multiple any late collisions) during transmission. collision packet counter (A060 0700) D31:12 D11:00 Incremented for each frame transmitted that experienced a late collision during a Transmit late transmission attempt. Late collisions are defined using the CWIN[13:08] field of the collision packet counter (A060 Collision Window/Retry register.
Page 310: Transmit Oversize Frame Counter (A060 0724)
Carry Register 2 Mask register (CAM2) have individual mask bits for each of the carry bits. When set, the mask bit prevents the associated carry bit from setting the STOVFL bit. Address: A060 0730 Carry Register 1 Hardware Reference NS9215 and contains a valid FCS. (VLAN) Reset = Read as 0 Reserved...
Page 311: Carry Register 2
Register C164 C1127 Register bit Bits assignment D24:17 Address: A060 0734 Carry Register 2 www.digiembedded.com E T H E R N E T C O M M U N I C A T I O N M O D U L E C1255 C1511 C11K C1RXP...
Page 312: Carry Register 1 Mask Register
E T H E R N E T C O M M U N I C A T I O N M O D U L E Statistics registers Register Register bit Bits Access assignment D31:20 D01:00 Address: A060 0738 Carry Register 1 Mask register Hardware Reference NS9215 Reserved C2TMC C2TBC Rsvd C2TDF Mnemonic Reset Description Reserved C2TJB Carry register 2 TJBR counter carry bit...
Page 313 Register M164 M1127 Register bit Bits assignment D24:17 www.digiembedded.com E T H E R N E T C O M M U N I C A T I O N M O D U L E 1255 1511 C11K M1RXP M1RAL Access Mnemonic...
Page 314: Carry Register 2 Mask Register
E T H E R N E T C O M M U N I C A T I O N M O D U L E Statistics registers Address: A060 073C Carry Register 2 Mask register Register Register bit Bits Access assignment D31:20 D01:00 Hardware Reference NS9215 Reserved M2TBC M2TDF used Mnemonic Reset Description Reserved M2TJB Mask register 2 TJBR counter carry bit mask M2TFC...
Page 315: Rx_A Buffer Descriptor Pointer Register
R X _ A B u f f e r D e s c r i p t o r P o i n t e r r e g i s t e r ................. . Address: A060 0A00 Register Register bit...
Page 316: Rx_C Buffer Descriptor Pointer Register
................. . Address: A060 0A0C Register Register bit Bits Access assignment D31:00 Hardware Reference NS9215 RXCPTR RXCPTR Mnemonic Reset Description RXCPTR 0x00000000...
Page 317: Ethernet Interrupt Status Register
E t h e r n e t I n t e r r u p t S t a t u s r e g i s t e r ................. . Address: A060 0A10 The Ethernet Interrupt Status register contains status bits for all of the Ethernet interrupt sources.
Page 318 E T H E R N E T C O M M U N I C A T I O N M O D U L E Ethernet Interrupt Status register Bits Access D15:07 Hardware Reference NS9215 Mnemonic Reset Description RXDONEB Assigned to RX interrupt.
Page 319: Ethernet Interrupt Enable Register
Bits E t h e r n e t I n t e r r u p t E n a b l e r e g i s t e r ................. . Address: A060 0A14 The Ethernet Interrupt Enable register contains individual enable bits for each of the bits in the Ethernet Interrupt Status register.
Page 320: Tx Buffer Descriptor Pointer Register
................. . Address: A060 0A18 Register Register bit Bits Access assignment D31:08 D07:00 Hardware Reference NS9215 Mnemonic Reset Description EN_RXBR Enable the RXBR interrupt bit. Reserved EN_STOVFL Enable the STOVFL interrupt bit.
Page 321: Transmit Recover Buffer Descriptor Pointer Register
T r a n s m i t R e c o v e r B u f f e r D e s c r i p t o r P o i n t e r r e g i s t e r .
Page 322: Tx Stall Buffer Descriptor Pointer Register
................. . Address: A060 0A24 Register Hardware Reference NS9215 Mnemonic Reset...
Page 323: Rx_A Buffer Descriptor Pointer Offset Register
Register bit Bits assignment D31:08 D07:00 R X _ A B u f f e r D e s c r i p t o r P o i n t e r O f f s e t r e g i s t e r .
Page 324: Rx_B Buffer Descriptor Pointer Offset Register
................. . Address: A060 0A30 Register Reserved Hardware Reference NS9215 Reserved Mnemonic Reset...
Page 325: Rx_D Buffer Descriptor Pointer Offset Register
Register bit Bits assignment D31:11 D10:00 R X _ D B u f f e r D e s c r i p t o r P o i n t e r O f f s e t r e g i s t e r .
Page 326: Rx Free Buffer Register
RXFREE has an individual bit for each pool; this bit is set to 1 when the register is written. Reads to RXFREE always return all 0s. Register Register bit Bits Access assignment D31:04 Hardware Reference NS9215 Reserved Reserved Mnemonic Reset Description Reserved TXOFF...
Page 327: Multicast Address Filter Registers
Bits M u l t i c a s t A d d r e s s F i l t e r r e g i s t e r s ................. . Each of the eight entries in the multicast address filter logic has individual registers to hold its 48-bit multicast address.
Page 328: Multicast Low Address Filter Register #6
D15:00 Address: A060 0A74 Multicast High Address Filter Register #5 D31:16 D15:00 Hardware Reference NS9215 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000...
Page 329: Multicast High Address Filter Register #6
Address: A060 0A78 Multicast High Address Filter Register #6 D31:16 D15:00 Address: A060 0A7C Multicast High Address Filter Register #7 D31:16 D15:00 M u l t i c a s t A d d r e s s M a s k r e g i s t e r s .
Page 330: Multicast Low Address Mask Register #4
D31:16 D15:00 Address: A060 0AB0 Multicast High Address Mask Register #4 D31:16 Hardware Reference NS9215 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000 Default = 0x0000 0000...
Page 331: Multicast High Address Mask Register #5
D15:00 Address: A060 0AB4 Multicast High Address Mask Register #5 D31:16 D15:00 Address: A060 0AB8 Multicast High Address Mask Register #6 D31:16 D15:00 Address: A060 0ABC Multicast High Address Mask Register #7 D31:16 D15:00 M u l t i c a s t A d d r e s s F i l t e r E n a b l e r e g i s t e r .
Page 332: Tx Buffer Descriptor Ram
The TX buffer descriptor RAM holds 64 transmit buffer descriptors on-chip. Each buffer descriptor occupies four locations in the RAM, and the RAM is implemented as a 256x32 device. This is the format of the TX buffer descriptor RAM: Offset+0 D31:00 Hardware Reference NS9215 Mnemonic Reset Reserved MFILTEN7...
Page 333: Offset+4
Offset+4 D31:11 D10:00 Offset+8 D31:00 Offset+C D27:16 D15:00 See “Transmit buffer descriptor format” on page 270, for more information about the fields in Offset+C. R X F I F O R A M ................. . Address: A060 2000 (512 locations) The 2k Byte RX FIFO RAM can be used by the CPU as a scratch pad memory during boot up.
Page 334: Sample Hash Table Code
* into the registers HT1 and HT2. * Parameters: none * Return Values: none static void eth_load_mca_table (void) WORD32 has_table[2]; // create hash table for MAC address eth_make_hash_table (hash_table); Hardware Reference NS9215 /*list of MCA addresses*/ /*# of MCA addresses*/...
Page 335 * Function: void eth_make_hash_table (WORD32 *hash_table) * Description: Parameters: * Return Values: static void eth_make_hash_table (WORD32 *hash_table) int index; memset (hash_table, 0, 8); for (index = 0; index < mca_count; index++) www.digiembedded.com E T H E R N E T C O M M U N I C A T I O N M O D U L E (*MERCURY_EFE).ht2.bits.data = SWAP32(hash_table[1]);...
Page 336 This routine calculates which bit in the CRC hash table needs to be set for the MERCURY to recognize incoming packets with the MCA passed to us. * Parameters: Hardware Reference NS9215 pointer to hash table position of bit to set pointer to multi-cast address...
Page 337 * Return Values: #define POLYNOMIAL 0x4c11db6L static int calculate_hash_bit (BYTE *mca) WORD32 crc; WORD16 *mcap, bp, bx; int result, index, mca_word, bit_index; BYTE lsb; WORD16 copy_mca[3] memcpy (copy_mca,mca,sizeof(copy_mca)); for (index = 0; index < 3; index++) mcap = copy_mca; crc = 0xffffffffL; for (mca_word = 0;...
Page 338 E T H E R N E T C O M M U N I C A T I O N M O D U L E Sample hash table code // CRC calculation done. The 6-bit result resides in bit // locations 28:23 result = (crc >> 23) & 0x3f; return result; Hardware Reference NS9215 bp = rotate (bp, RIGHT, 1);...
Page 339: Dma Transfers
External DMA he external DMA interface provides two external channels for external peripheral support. Each DMA channel moves data from the source address to the destination address. These addresses can specify any peripheral on the AHB bus but, ideally, they specify an external peripheral and external memory. D M A t r a n s f e r s .
Page 340: Dma Buffer Descriptor
The address [pointer] destination address can be aligned to any byte boundary. Hardware Reference NS9215 A DMA channel configured for more than the maximum number of buffer descriptors operates in an unpredictable fashion.
Page 341: Status
Optimal performance is achieved when the destination address is aligned on a Note: word boundary. This field is not used. Read back 0x0000. Status The Wrap (W) bit, when set, tells the DMA controller that this is the last buffer Wrap (W) bit descriptor within the continuous list of descriptors.
Page 342: Peripheral Dma Read Access
PDEN be computed correctly and programmed in the static memory controllers. Use this equation to compute total access time: Total access time = T Equation Variable variables Hardware Reference NS9215 signals. st_cs_n[n] st_oe_n + 10.0 Definition Peripheral read access time...
Page 343: Peripheral Dma Single Read Access
Peripheral DMA single read access st_cs_n[n] st_oe_n ADDR PDEN Peripheral DMA burst read access st_cs_n[n] st_oe_n ADDR PDEN P e r i p h e r a l D M A w r i t e a c c e s s .
Page 344: Determining The Width Of Pden
REQ signal. The REQ signal can be deasserted during a transfer but if the peripheral is configured for burst access, the burst completes. The DMA transfer control logic remains paused until the REQ signal is reasserted. Hardware Reference NS9215 ADDR1/DATA1 ADDR2/DATA2...
Page 345: Done Signal
The external peripheral can terminate the DMA transfer at any time by DONE signal asserting the DONE signal. The peripheral must also deassert the REQ signal when it asserts the DONE signal. The DONE signal can be asserted during a transfer but if the peripheral is configured for burst access, the burst completes.
Page 346: Control And Status Registers
The DMA Buffer Descriptor Pointer register contains a 32-bit pointer to the first buffer in a contiguous list of buffer descriptors. The external DMA module has two of these registers. Each buffer descriptor is 16 bytes in length. Hardware Reference NS9215 Field Value Comment...
Page 347: Dma Control Register
Register Register bit Bit(s) assignment D31:00 D M A C o n t r o l r e g i s t e r ................. . Address: A080_0004, A080_0014 The DMA Control register contains the required DMA transfer control information.
Page 348 Register bit Bit(s) Access assignment D28:27 D26:25 D24:23 Hardware Reference NS9215 Mnemonic Reset Description Channel enable Enables and disables DMA operations as required. After a DMA channel has entered the IDLE state for any reason, this field must be written to a 1 to initiate further DMA transfers.
Page 349 Bit(s) D22:21 www.digiembedded.com Access Mnemonic Reset SINC_N DINC_N MODE E X T E R N A L D M A DMA Control register Description Destination burst Defines the AHB maximum burst size allowed when writing to the destination. Note that the destination must have enough space, as defined by this register setting, before asserting REQ.
Page 350: Dma Status And Interrupt Enable Register
AHB DMA interrupt signals. The external DMA module has two of these registers. Register NCIP ECIP NRIP Hardware Reference NS9215 Mnemonic Reset Description Reset Forces a reset of the DMA channel. Writing a 1 to this field forces all fields in this register, except the index field, to the reset state.
Page 351 Register bit Bit(s) assignment D26:25 www.digiembedded.com Access Mnemonic Reset R/W1C NCIP R/W1C ECIP R/W1C NRIP R/W1C CAIP R/W1C PCIP Not used E X T E R N A L D M A DMA Status and Interrupt Enable register Description Normal completion interrupt pending Set when a buffer descriptor has been closed.
Page 352: Dma Peripheral Chip Select Register
................. . Address: A080_000C, A080_001C The DMA Peripheral Chip Select register contains the DMA channel peripheral chip select definition. The external DMA module has two of these registers. Register Hardware Reference NS9215 Mnemonic Reset Description NCIE Enable NCIP interrupt generation.
Page 353 Register bit Bit(s) assignment D31:02 D01:00 www.digiembedded.com Access Mnemonic Reset Not used E X T E R N A L D M A DMA Peripheral Chip Select register Definition This field must always be set to 0. Chip select Defines which of the four memory interface chip select signals (nmpmcstcsout[n]) is connected to the external peripheral.
Page 354 E X T E R N A L D M A DMA Peripheral Chip Select register Hardware Reference NS9215...
Page 355: Features
AES Data Encryption/Decryption Module he AES data encryption/decryption module provides IPSec-compatible network security to processor-based systems. The AES core module implements Rijndael encoding/decoding in compliance with the NIST Advanced Encryption Standard (AES). Processes 32 bits at a time. Features Is programmable for 128-, 192-, or 256-bit key lengths. Supports ECB, CBC, OFB, CTR, and CCM cipher modes.
Page 356: Block Diagram
................. . The AES DMA buffer descriptor is the same as the external DMA buffer descriptor, with the exception of the control bits — AES op and AES control. Hardware Reference NS9215 Mode and Control Expanded Key...
Page 357: Aes Buffer Descriptor Diagram
AES buffer descriptor diagram OFFSET + 0 OFFSET + 4 OFFSET + OFFSET + C Field definitions follow. The source address pointer identifies the starting location of the source data. The Source address source address can be aligned to any byte boundary. [pointer] Optimal performance is achieved when the source address is aligned on a Note:...
Page 358: Aes Op Code
The Full bit, when set, indicates that the buffer descriptor is valid and can be Full (F) bit processed by the DMA channel. The DMA channel clears this bit after completing the transfer(s). Hardware Reference NS9215 Values 128 bits 192 bits...
Page 359: Decryption
The DMA channel does not try a transfer when the F bit is clear. The DMA channel enters an idle state upon fetching a buffer descriptor with the F bit cleared. When the F bit is modified by the device driver, the device driver must also write an ‘I’...
Page 360: Cbc, Cfb, Ofb, And Ctr Processing
................. . CCM mode does not require an initialization vector. Hardware Reference NS9215 ECB Mode...
Page 361: Nonce Buffer
For encryption, software must set up this buffer descriptor sequence: Key, Nonce, additional data (optional), data (used to compute the authentication code), data (used to perform the actual encryption). For decryption, software must set up this buffer descriptor sequence: Key, Nonce, Data (used to perform the actual decryption), Additional data (optional), Data (used to compute the authentication code).
Page 362 A E S D A T A E N C R Y P T I O N / D E C R Y P T I O N M O D U L E CCM mode Hardware Reference NS9215...
Page 363 I/O Hub Module he I/O hub provides access to the low speed ports on the processor through one master port on the AHB bus. The low speed ports include four UART ports, one SPI port, one I (A/D) port. UART channel C can be configured for HDLC operation. The SPI, UART, and A/D ports can be controlled either directly by the CPU or through the DMA controller, which is integrated into the I/O hub, The I have DMA support.
Page 364: Block Diagram
FIFOs needs servicing — that is, it can accept a burst of four 32-bit words — the FIFOs DMA controller requests the AHB bus through the AHB master. After the request has been granted, the peripheral buffer data is transferred to or from system memory. Hardware Reference NS9215 AMBA AHB Bus AHB Master DMA Controller...
Page 365: Buffer Descriptors
The peripheral buffer data is held in buffers in external memory, linked together Buffer descriptors using buffer descriptors. The buffer descriptors are 16 bytes in length and are located contiguously in external memory. This is the format of the buffer descriptor: Address offset + 0 offset + 4...
Page 366: Control[11:0]
In direct mode, the status can be read from the Direct Mode RX Status FIFO. Note: UART Bits 15:7 Hardware Reference NS9215 Description Reserved Error; bits 3:0 indicate the error type bit 4: Reserved bit 3: Receiver overflow, should never occur in a properly configured system...
Page 367: Transmit Dma Example
HDLC Bits 15:7 Not applicable. T r a n s m i t D M A e x a m p l e ................. . After the last buffer in the data packet has been placed in system memory and the buffer descriptors have been configured, the data packet is ready to be transmitted.
Page 368: Visual Example
MMU must be disabled for all registers in the I/O Hub address space, from address 0x9000_0000 to 0x9FFF_FFFF. Register address maps are shown for each low speed peripheral module. Hardware Reference NS9215 System Memory Buffer Pointer = null...
Page 369: Register Offset
Registers 9000_0000 – 9000_7FFF and registers 9000_8000 – 9000_FFFF are Note: reserved. UART A register Register Offset address map 0x9001_0000 0x9001_0004 0x9001_0008 0x9001_000C 0x9001_0010 0x9001_0014 0x9001_0018 0x9001_001C 0x9001_0020 0x9001_0024 0x9001_0028 0x9001_002C 0x9001_0030 – 0x9001_0FFF 0x9001_1000 – 0x9001_7FFF UART B register Register Offset address map 0x9001_8000...
Page 370: Uart C Register Address Map
0x9002_8010 0x9002_8014 0x9002_8018 0x9002_801C 0x9002_8020 0x9002_8024 0x9002_8028 0x9002_802C Hardware Reference NS9215 Description (31:00) Reserved UART B CSR Space Description (31:00) UART C Interrupt and FIFO Status UART C DMA RX Control UART C DMA RX Buffer Descriptor Pointer UART C DMA RX Interrupt Configuration register...
Page 371: Spi Register Address Map
Register Offset 0x9002_8030 – 0x9002_8FFF 0x9002_9000 – 0x9002_FFFF SPI register Register Offset address map 0x9003_0000 0x9003_0004 0x9003_0008 0x9003_000C 0x9003_0010 0x9003_0014 0x9003_0018 0x9003_001C 0x9003_0020 0x9003_0024 0x9003_0028 0x9003_002C 0x9003_0030 – 0x9003_0FFF 0x9003_1000 – 0x9003_7FFF AD register Register Offset address map 0x9003_8000 – 0x9003_8FFF 0x9003_9000 –...
Page 372: Rtc Register Address Map
An access type of R/W* means that the processor must write 1 to clear the Note: value if the read value is 1. If the read value is 0, the write value must be 0. Hardware Reference NS9215 Description (31:00) RTC CSR Space...
Page 373 Register R X N R X E C IP C IP R X PB FIFO U S Y full Register bit Bit(s) assignment www.digiembedded.com R X N R X C R X P R X F R X FS TX N R IP A IP C IP...
Page 374 [Module] Interrupt and FIFO Status register Bit(s) Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Hardware Reference NS9215 Mnemonic Reset Description RXFOFIP RX FIFO overflow interrupt pending Set when the RX FIFO finds an overflow condition. RXFSRIP RX FIFO service request interrupt pending (RX)
Page 375: [Module] Dma Rx Control
Bit(s) D17:16 D09:00 [ M o d u l e ] D M A R X C o n t r o l ................. . Addresses: 9000_0004 / 9000_8004 / 9001_0004 / 9001_8004 / 9002_0004 / 9002_8004 / 9003_0004 / 9003_8004 The DMA RX Control register contains control register settings for each receive DMA...
Page 376: [Module] Dma Rx Buffer Descriptor Pointer
Addresses: 9000_0008 / 9000_8008 / 9001_0008 / 9001_8008 / 9002_0008 / 9002_8008 / 9003_0008 / 9003_8008 The DMA RX Buffer Descriptor Pointer register is the address of the first buffer descriptor for each DMA channel. Hardware Reference NS9215 FLEX DIRECT Reserved...
Page 377: [Module] Rx Interrupt Configuration Register
Register Register bit Bit(s) assignment D31:00 [ M o d u l e ] R X I n t e r r u p t C o n f i g u r a t i o n r e g i s t e r .
Page 378: [Module] Direct Mode Rx Status Fifo
This register must be read before each read to the RX Data FIFO register. The RX Data FIFO register must be read after each read to this register, even if the BYTE field is 0. Register Reserved Hardware Reference NS9215 Mnemonic Reset Description RXFOFIE Enable the RXFOFIP interrupt.
Page 379: [Module] Direct Mode Rx Data Fifo
Register bit Bit(s) assignment D31:12 D11:09 D06:00 [ M o d u l e ] D i r e c t M o d e R X D a t a F I F O ................. . Addresses: 9000_0014 / 9000_8014 / 9001_0014 / 9001_8014 / 9002_0014 / 9002_8014 / 9003_0014 / 9003_8014 The Direct Mode RX Data FIFO register is used when in direct mode of operation, to...
Page 380: [Module] Dma Tx Control
The DMA TX Control register contains control register settings for each transmit DMA channel. Register STATE Register bit Bit(s) Access assignment D26:16 D15:10 D09:00 Hardware Reference NS9215 FLEX Reserved DIRECT INDEXEN Mnemonic Reset Description Channel enable Channel abort When set, causes the current DMA operation to complete and closes the buffer.
Page 381: [Module] Dma Tx Buffer Descriptor Pointer
[ M o d u l e ] D M A T X B u f f e r D e s c r i p t o r P o i n t e r ................. . Addresses: 9000_001C / 9000_801C / 9001_001C / 9001_801C / 9002_001C / 9002_801C / 9003_001C The DMA TX Buffer Descriptor Pointer is the address of the first buffer descriptor for...
Page 382: [Module] Direct Mode Tx Data Fifo
9002_8028 / 9003_0028 The Direct Mode TX Data FIFO register is used when in direct mode of operation, to write the TX data FIFO. The write can be 8-, 16-, or 32-bit. Register Hardware Reference NS9215 Mnemonic Reset Description TXTHRS...
Page 383: [Module] Direct Mode Tx Data Last Fifo
Register bit Bit(s) assignment D31:00 [ M o d u l e ] D i r e c t M o d e T X D a t a L a s t F I F O ................. . Addresses: 9000_002C / 9000_802C / 9001_002C /9001_802C / 9002_002C / 9000_802C / 9003_002C The Direct Mode TX Data LAst FIFO register is used when in direct mode of...
Page 384 I / O H U B M O D U L E [Module] Direct Mode TX Data Last FIFO Hardware Reference NS9215 31 March 2008...
Page 385: Features
Serial Control Module: UART he processor ASIC supports four independent universal asynchronous receiver/transmitter (UART) channels (A through D). Each channel supports several modes, conditions, and formats. DMA transfers to and from system memory Features Independent receive and transmit programmable bit-rate generators High speed data transfer up to 1.8432 Mbps –...
Page 386: Uart Module Structure
Any field not specified in this table can be left at reset value. configuration Control register UART Line Control register (0x10c) UART Baud Rate Divisor LSB (0x100) UART Line Control register (0x10c) UART FIFO Control register (0x108) FIFOEN Hardware Reference NS9215 UART Transmit Receive FIFO FIFO Interface Interface...
Page 387: Baud Rate Generator
Control register UART Interrupt Enable register (0x104) Wrapper Configuration register B a u d r a t e g e n e r a t o r ................. . The baud rate clock is generated by dividing the system reference clock by a programmable divisor;...
Page 388: Hardware-Based Flow Control
................. . UART provides a mechanism in which you can bypass data in the transmit FIFO with a specific character. The specified character is transmitted after the current Hardware Reference NS9215 Field Value...
Page 389: Force Character Transmission Procedure
character completes, regardless of any flow control mechanism that might stall normal data transmission. Use the Force Transmit Character Control register to program this operation. These steps outline a single force character transmission operation: Force character transmission Read the Force Transmit Character Control register and verify that the ENABLE procedure field is 0.
Page 390: Wrapper Control And Status Registers
9001_1100 DLAB=1 9001_1104 DLAB=0 9001_1104 DLAB=1 9001_1108 9001_110C 9001_1110 Hardware Reference NS9215 Register Wrapper Configuration Interrupt Enable Interrupt Status Receive Character GAP Control Receive Buffer GAP Control Receive Character Match Control 0 Receive Character Match Control 1 Receive Character Match Control 2...
Page 391: Wrapper Configuration Register
Address 9001_1114 9001_1118 9001_111C W r a p p e r C o n f i g u r a t i o n r e g i s t e r ................. . Address: 9001_1000 / 9001_9000 / 9002_1000 / 9002_9000 This is the primary Wrapper Configuration register.
Page 392 S E R I A L C O N T R O L M O D U L E : U A R T Wrapper Configuration register Bits Access D15:14 D11:06 Hardware Reference NS9215 Mnemonic Reset Description RXFLUSH Resets the contents of the 64-byte RXFIFO.
Page 393: Interrupt Enable Register
Bits D03:02 D01:00 I n t e r r u p t E n a b l e r e g i s t e r ................. . Address: 9001_1004 / 9001_9004 / 9002_1004 / 9002_9004 Use the Interrupt Enable register to enable interrupt generation on specific events.
Page 394 S E R I A L C O N T R O L M O D U L E : U A R T Interrupt Enable register Bits Access Hardware Reference NS9215 Mnemonic Reset Description OFLOW Enable overflow error Enables interrupt generation if the 4-character FIFO in the UART overflows.
Page 395: Interrupt Status Register
Bits I n t e r r u p t S t a t u s r e g i s t e r ................. . Address: 9001_1008 / 9001_9008 / 9002_1008 / 9002_9008 The Interrupt Status register provides status about UART events.
Page 396 Register bit Bits Access assignment D31:22 R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC Hardware Reference NS9215 Not used MATCH MATCH MATCH MATCH MATCH CGAP Mnemonic Reset Description Not used Write this field to 0. Reserved UART interrupt Indicates that the UART has generated an interrupt.
Page 397 Bits www.digiembedded.com Access Mnemonic Reset Description R/W1TC MATCH3 Character match3 Indicates that a receive character match has occurred against the Receive Match Register 3. R/W1TC MATCH2 Character match2 Indicates that a receive character match has occurred against the Receive Match Register 2. R/W1TC MATCH1 Character match1...
Page 398: Receive Character Gap Control Register
REGISTER Register Register bit Bits Access assignment D30:25 D24:00 Hardware Reference NS9215 Mnemonic Reset Description TX_IDLE Transmit idle Indicates that the transmitter has moved from the active state to the idle state. The transmitter moves from the active state to the idle state when the transmit FIFO is empty and the transmitter is not actively shifting out data.
Page 399: Receive Buffer Gap Control Register
R e c e i v e B u f f e r G A P C o n t r o l r e g i s t e r ................. . Address: 9001_1010 / 9001_9010 / 9002_1010 / 9002_9010 The Receive Buffer GAP Control register configures the receive buffer gap control logic.
Page 400: Receive Character-Based Flow Control Register
Use this register in conjunction with the Receive Character Match Control registers to define the flow control characters. If enabled, this function’s output is wired to the UART module instead of the CTS signal. Hardware Reference NS9215 Not used VALUE Mnemonic...
Page 401 Caution:Be aware that if multiple matches occur, an XOFF assertion will supersede an XON assertion. Register ABLE Register bit Bits assignment D31:11 D09:08 D07:06 www.digiembedded.com Not used Not used Access Mnemonic Reset Not used FLOW_STATE FLOW4 FLOW3 S E R I A L C O N T R O L M O D U L E : U A R T Receive Character-Based Flow Control register MASK DATA...
Page 402: Force Transmit Character Control Register
................. . Address: 9001_102C / 9001_902C / 9002_102C / 9002_902C Use the Force Transmit Character Control register to override the normal flow of transmit data. Hardware Reference NS9215 Mnemonic Reset Description...
Page 403: Arm Wakeup Control Register
Register BUSY ABLE Register bit Bits assignment D29:08 D07:00 A R M W a k e u p C o n t r o l r e g i s t e r ................. . Address: 9001_1030 / 9001_9030 / 9002_1030 / 9002_9030 Use the ARM Wakeup Control register to enable the ARM wakeup control logic.
Page 404: Transmit Byte Count
................. . Address: 9001_1034 / 9001_9034 / 9002_1034 / 9002_9034 Register A BLE Register bit Bits Access assignment D30:24 D23:00 Hardware Reference NS9215 Not used Not used Mnemonic Reset Description Not used Write this field to 0. ENABLE Enable Write a 1 to this field to enable ARM wakeup control logic.
Page 405: Uart Receive Buffer
U A R T R e c e i v e B u f f e r ................. . Address: 9001_1100 / 9001_9100 / 9002_1100 / 9002_9100, DLAB = 0, Read UART Receive Buffer is used for diagnostic purposes only.
Page 406: Uart Baud Rate Divisor Lsb
................. . Address: 9001_1104 / 9001_9104 / 9002_1104 / 9002_9104, DLAB = 1 UART Baud Rate Divisor sets bits 15:08 of the baud rate generator divisor. Hardware Reference NS9215 Mnemonic Reset...
Page 407: Uart Interrupt Enable Register
Register Register bit Bits assignment D31:08 D07:00 U A R T I n t e r r u p t E n a b l e r e g i s t e r ................. . Address: 9001_1104 / 9001_9104 / 9002_1104 / 9002_9104, DLAB = 0 The UART Interrupt Enable register selects the source of the interrupt from the UART.
Page 408: Uart Interrupt Identification Register
The UART Interrupt Identification register reads the source of the interrupt from the UART. This register is for diagnostic purposes only. Register Register bit Bits Access assignment D31:04 D03:00 Hardware Reference NS9215 Mnemonic Reset Description ELSI Enables receive line status interrupt Disabled Enabled ETBEI...
Page 409: Uart Fifo Control Register
U A R T F I F O C o n t r o l r e g i s t e r ................. . Address: 9001_1108 / 9001_9108 / 9002_1108 / 9002_9108, Write The UART FIFO Control register controls the RX and TX 4-byte FIFOs.
Page 410 S E R I A L C O N T R O L M O D U L E : U A R T UART Line Control register Register Register bit Bits Access assignment D31:08 D01:00 Hardware Reference NS9215 Reserved Reserved D LA B Mnemonic Reset Description Reserved DLAB...
Page 411: Uart Modem Control Register
U A R T M o d e m C o n t r o l r e g i s t e r ................. . Address: 9001_1110 / 9001_9110 / 9002_1110 / 9002_9110 The UART Modem Control register controls the modem signals.
Page 412: Uart Modem Status Register
................. . Address: 9001_1118 / 9001_9118 / 9002_1118 / 9002_9118 The UART Modem Status register reads the modem status register. This register is used for diagnostic purposes only. Hardware Reference NS9215 Reserved Reserved FIER...
Page 413 Register Register bit Bits assignment D31:08 www.digiembedded.com Reserved Reserved Access Mnemonic Reset Description Reserved Reflects the status of the data carrier detect input. Reflects the status of the ring indicator. Reflects the status of the data set ready input. Reflects the status of the clear to send input. DDCD Delta DCD indicator Indicates that an edge was found on DCD since the last...
Page 414 S E R I A L C O N T R O L M O D U L E : U A R T UART Modem Status register Hardware Reference NS9215...
Page 415: Hdlc Module Structure
Serial Control Module: HDLC he HDLC module allows full-duplex synchronous communication. Both the receiver and transmitter can select either an internal or external clock. The HDLC module encapsulates data within opening and closing flags, and sixteen bits of CRC precedes the closing flag. All information between the opening and closing flag is zero-stuffed;...
Page 416: Receive Operation
“byte” in the frame is not eight bits, the receiver sets a status flag that is buffered along with this last byte. Software then uses the table shown next to determine the number of valid data bits in this last “byte.” Note that the receiver transfers all bits Hardware Reference NS9215...
Page 417: Last Byte Bit Pattern Table
between the opening and closing flags, except for the inserted zeroes, to the receiver data buffer. Last byte bit Last byte bit pattern pattern table bbbbbbb0 bbbbbb01 bbbbb011 bbbb0111 bbb01111 bb011111 b0111111 D a t a e n c o d i n g .
Page 418: Digital Phase-Locked-Loop (Dpll) Operation: Encoding
(for example, a long string of zeroes), but the other data encodings do. NRZI guarantees transitions because of inserted zeroes. The Biphase encodings all have at least one transition per bit cell. Hardware Reference NS9215...
Page 419: Dpll-Tracked Bit Cell Boundaries
The DPLL counter normally counts by 16 but if a transition occurs earlier or later than DPLL-tracked bit expected, the count is modified during the next count cycle. cell boundaries If the transition occurs earlier than expected, the bit cell boundaries are early with respect to the DPLL-tracked cell boundaries and the count is shortened by either one or two counts.
Page 420: Nrz And Nrzi Encoding
DPLL to synchronize faster to the data stream when starting With biphase-level encoding, there is a guaranteed “clock” transition at the center of Biphase-Level every bit-cell and optional “data” transitions at the bit-cell boundaries. The DPLL encoding Hardware Reference NS9215 add two subtract two subtract one none...
Page 421: Biphase-Mark And Biphase-Space Encoding
only uses the clock transitions to track the bit-cell boundaries, by ignoring all transitions occurring outside a window around the center of the bit-cell. The window is half a bit-cell wide. Because the clock transitions are guaranteed, the DPLL requires that they always be present.
Page 422: Wrapper And Hdlc Control And Status Registers
................. . Address: 9002_9000 This is the primary Wrapper Configuration register. Hardware Reference NS9215 Field Value...
Page 423 Register Reserv RXEN RXBYTES Register bit Bits assignment D27:18 D15:14 D11:06 www.digiembedded.com TXEN MODE Reserved Reserved CLOSE Access Mnemonic Reset Description Reserved RXEN TXEN MODE Applies only to UART channel C. Reserved RXFLUSH Resets the contents of the 64-byte RXFIFO. Write a 1, then a 0 to reset the FIFO.
Page 424: Interrupt Enable Register
Reserv RXCLS Register bit Bits Access assignment D31:22 Hardware Reference NS9215 Mnemonic Reset Description Local loopback Provides an internal local loopback feature. When the LL field is set to 1, the transmit HDLC data signal is connected to the receive HDLC data signal.
Page 425: Interrupt Status Register
Bits D13:04 I n t e r r u p t S t a t u s r e g i s t e r ................. . Address: 9002_9008 The Interrupt Status register provides status about HDLC events.
Page 426 Access assignment D31:22 R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC D13:04 R/W1TC R/W1TC Hardware Reference NS9215 Not used Reserved Mnemonic Reset Description Not used Write this field to 0. HINT HDLC interrupt Indicates that the HDLC has generated an interrupt. Reserved...
Page 427: Hdlc Data Register 1
Bits H D L C D a t a R e g i s t e r 1 ................. . Address: 9002_9100 HDLC Data Register 1 reads data from the receive buffer and load data in the transmit buffer.
Page 428: Hdlc Data Register 3
HDLC Data Register 3 writes the last byte of data of a frame after which the closing flag is transmitted. This register is for debug purposes only. Register Register bit Bits Access assignment D31:08 D07:00 Hardware Reference NS9215 Reserved Reserved Mnemonic Reset Description Reserved HDATA Read...
Page 429: Hdlc Control Register 1
H D L C C o n t r o l R e g i s t e r 1 ................. . Address: 9002_9110 HDLC Control Register 1 configures the HDLC transmitter and receiver.
Page 430: Hdlc Clock Divider Low
................. . Address: 9002_9118 Hardware Reference NS9215 Reserved...
Page 431: Hdlc Clock Divider High
Use the HDLC CLock Divider Low register to set bits 07:00 of the clock divider. This is the equation for the HDLC clock rate: HDLC rate (bps) = Register Register bit Bits assignment D31:08 D07:00 H D L C C l o c k D i v i d e r H i g h .
Page 432 S E R I A L C O N T R O L M O D U L E : H D L C HDLC Clock Divider High Register bit Bits Access assignment D31:08 D06:00 Hardware Reference NS9215 Mnemonic Reset Description Not used Write this field to 0. Clock enable Must be set when the internal clock is used.
Page 433: Features
Serial Control Module: SPI he processor ASIC contains a single high speed, four-wire, serial peripheral interface (SPI) module. DMA transfers to and from system memory Features Four-wire interface (RXD, TXD, CLK, CS) Multi-drop supported through GPIO programming Master or slave operation High speed data transfer –...
Page 434: Spi Module Structure
The SPI port can operate in full-duplex mode. Information transfer is controlled by a Full duplex single clock signal. The clock and chip select signals are chip outputs for a master operation mode operation and inputs for a slave mode operation. Hardware Reference NS9215 Transmit State Machine Clock...
Page 435: Spi Clocking Modes
S P I c l o c k i n g m o d e s ................. . There are four SPI clocking modes.
Page 436: Spi Clock Generation
SPI interface. The boot-over-SPI hardware interfaces to devices requiring an 8-bit address, 16-bit address, or 24-bit address. The address width is indicated by strapping pins boot_mode[1:0] Hardware Reference NS9215 Data rate DIVISOR 33 Mbps 0x009...
Page 437: Available Strapping Options
Available boot_mode[1:0] strapping options The boot-over-SPI hardware requires several pieces of user-supplied information to EEPROM/FLASH complete the boot operation. This information must be located in a 128-byte header header starting at address zero in the external memory device. Each entry in the header is four bytes long.
Page 438: Time To Completion
In the second step, the hardware fetches the image at the user-specified data rate. Calculate time to completion for this step as shown: For example, with a 20 Mbps data rate and a 256 KB (2Mb) image, the time to completion is approximately 105ms. Hardware Reference NS9215 Name Description DynamicRefresh See the Memory Controller chapter.
Page 439: Spi Control And Status Registers
S P I C o n t r o l a n d S t a t u s r e g i s t e r s ................. . The configuration registers for the SPI module are located at 0x9003_1000.
Page 440: Clock Generation Register
................. . Address: 9003_1010 Hardware Reference NS9215 Mnemonic...
Page 441: Register Programming Steps
Use this register to define the data rate of the interface. This register must be programmed in three steps. Failure to follow these steps can result in unpredictable behavior of the SPI module. Set the ENABLE field to 0. The DIVISOR field must not be changed. Register programming Set the DIVISOR field to the value you want.
Page 442: Interrupt Status Register
................. . Address: 9003_1024 The Interrupt Status register provides status about SPI events. All events are indicated by reading a 1 and are cleared by writing a 1. Hardware Reference NS9215 Not used Not used Mnemonic...
Page 443: Spi Timing Characteristics
Register Register bit Bits assignment D31:02 S P I t i m i n g c h a r a c t e r i s t i c s ................. . These are the guaranteed timing parameters for all four SPI clocking modes.
Page 444: Spi Master Timing Diagram
Data output setup to CLK rising Data output hold from CLK rising CLK falling to CS# rising CS# deassertion time Notes: The SPI slave interface clock duty cycle should be no worse than 60/40. Hardware Reference NS9215 S2 S3 Unit Notes...
Page 445: Spi Slave Timing Diagram
The numbers shown here are for a 7.5 Mhz SPI slave interface clock rate. The numbers shown here are for a 300 Mhz PLL output frequency. This value must be proportionally increased with a PLL output frequency decrease. This parameter does not depend on any clock frequency. SPI slave timing diagram Mode3...
Page 446 S E R I A L C O N T R O L M O D U L E : S P I SPI timing characteristics Hardware Reference NS9215...
Page 447: Overview
I2C Master/Slave Interface he I2C master/slave interface provides an interface between the ARM CPU and the I2C bus. The I2C master/slave interface basically is a parallel-to-serial and serial-to-parallel converter. The parallel data received from the ARM CPU has to be converted to an appropriate serial form to be transmitted to an external component using the I2C bus.
Page 448: Multi-Master Bus
The general call address is for addressing all devices connected to the I device can ignore this address by not issuing an acknowledgement. The meaning of the general call address is always specified in the second byte. Hardware Reference NS9215 Description General call address...
Page 449: I2C Command Interface
C c o m m a n d i n t e r f a c e ................. . The I C module converts parallel (8-bit) data to serial data and serial data to parallel data between the processor and the I...
Page 450: I2C Registers
The Command Transmit Data ( register for transmission of data between the I/O hub and I write only. Register PIPE DLEN Hardware Reference NS9215 interrupt is generated to the host processor and the command must are written simultaneously and CMD_REG are read simultaneously. Description...
Page 451: Register Bit Assignment
Register bit assignment Bits D31:16 D12:08 D07:00 S t a t u s R e c e i v e D a t a r e g i s t e r ................. . Address: 9005 0000 The Status Receive Data register ( register for receipt of data between the I/O hub and I...
Page 452: Master Address Register
................. . Address: 9005 0004 If using 7-bit addressing, the master device address field uses only bits D07:01; otherwise, all 10 bits are used. Register Reserved Hardware Reference NS9215 Access Mnemonic Reset SCMDL MCMDL...
Page 453: Register Bit Assignment
Register bit assignment Bits D10:01 S l a v e A d d r e s s r e g i s t e r ................. . Address: 9005 0008 If using 7-bit addressing, the slave device address field uses only bits D07:01;...
Page 454: Configuration Register
C_bus_clock = (4 / 3) x (clk / ((CLREF*2) + 4 + scl_delay)) is influenced by the SCL rise time. scl_delay Register IRQD TMDE Register bit assignment Bits D31:16 Hardware Reference NS9215 Reserved VSCD Access Mnemonic Reset Reserved IRQD TMDE VSCD C bus.
Page 455: Interrupt Codes
Bits D12:09 D08:00 I n t e r r u p t C o d e s ................. . Interrupts are signaled in the appropriate interrupt code (see “Master/slave interrupt codes”...
Page 456: Software Driver
C slave high transaction. After this command, the slave remains inactive until the next start level driver condition on the I S_TX_DATA distinguish the transactions from each other, special S_TX_DATA_1ST Hardware Reference NS9215 Master/slave Slave Slave Slave Slave Slave to start a read sequence...
Page 457: Flow Charts
F l o w c h a r t s ................. . Master module (normal mode, 16- bit)
Page 458: Slave Module (Normal Mode, 16-Bit)
I 2 C M A S T E R / S L A V E I N T E R F A C E Flow charts Slave module (normal mode, 16- bit) S_RX_ABORT STATUS_REG Note: Hardware Reference NS9215 wait irq read rx/status S_RX_DATA_1ST wait irq read rx/status...
Page 459: Real Time Clock Module
Real Time Clock Module he Real Time Clock (RTC) module tracks the time of the day to an accuracy of 10 milliseconds and provides calendar functionality that tracks day, month, and year. RTC monitors these time periods: RTC functionality Year from 1900-2999 Month from 1-12 Date from 1-28, 29, 30, or 31, as a function of year and month Day of week from 1-7...
Page 460: Rtc Configuration And Status Registers
................. . Address: 9006 0000 The RTC General Control register contains miscellaneous settings for the RTC module. Register Hardware Reference NS9215 Description RTC General Control register 12/24 Hour register Time register...
Page 461: 12/24 Hour Register
Register bit Bits assignment D31:02 1 2 / 2 4 H o u r r e g i s t e r ................. . Address: 9006 0004 The 12/24 Hour register controls 12 or 24 hour clock mode operation.
Page 462: Time Register
Register Rsvd Rsvd Register bit Bits assignment D29:28 D27:24 D22:20 D19:16 D14:12 D11:08 D07:04 D03:00 Hardware Reference NS9215 HR_T HR_U Rsvd Access Mnemonic Reset Reserved HR_T HR_U Reserved Reserved Description Used in 12 hour mode only. Hours, tens, BCD digit (0-2)
Page 463: Calendar Register
C a l e n d a r r e g i s t e r ................. . Address: 9006 000C The Calendar register sets the calendar values to the correct values, and reads the calendar registers.
Page 464: Time Alarm Register
Register Rsvd Rsvd Register bit Bits assignment D29:28 D27:24 D22:20 D19:16 D14:12 D11:08 D07:04 D03:00 Hardware Reference NS9215 HR_T HR_U Rsvd Access Mnemonic Reset Reserved HR_T HR_U Reserved Reserved Description Used in 12 hour mode only. Hours, tens, BCD digit (0-2)
Page 465: Calendar Alarm Register
C a l e n d a r A l a r m r e g i s t e r ................. . Address: 9006 0014 The Calendar Alarm register sets the calendar alarm.
Page 466: Event Flags Register
Read the register to determine the cause of the current active interrupt. This register is cleared when read (R/R in Access column). Note that the Event Flags register can change even if the corresponding alarm enable bit is not set. Hardware Reference NS9215 Reserved Reserved Access...
Page 467 Register Register bit Bits assignment D31:07 www.digiembedded.com Reserved Reserved Access Mnemonic Reset Reserved Alarm Mnth Evnt Date Evnt Hour Evnt Min Evnt Sec Evnt Hsec Evnt R E A L T I M E C L O C K M O D U L E Event Flags register Mnth Date...
Page 468: Interrupt Enable Register
The Interrupt Enable register sets which events can generate and interrupt. The interrupt that is generated remains set until it is cleared by disabling the event or by reading/clearing the Event Flags register. Register Register bit Bits assignment D31:07 Hardware Reference NS9215 Reserved Reserved Access Mnemonic Reset Reserved Alrm Int...
Page 469: Interrupt Disable Register
I n t e r r u p t D i s a b l e r e g i s t e r ................. . Address: 9006 0024 The Interrupt Disable register resets interrupts that are currently enables.
Page 470: Interrupt Enable Status Register
................. . Address: 9006 0028 The Interrupt Enable Status register determines which interrupt sources are enabled and which interrupt sources are disabled. Register Register bit Bits assignment D31:07 Hardware Reference NS9215 Reserved Reserved Access Mnemonic Reset Reserved Alrm Stat Mnth Stat...
Page 471: General Status Register
G e n e r a l S t a t u s r e g i s t e r ................. . Address: 9006 002C The General Status register determines the status of the RTC configuration.
Page 472 R E A L T I M E C L O C K M O D U L E General Status register Hardware Reference NS9215...
Page 473: Analog-To-Digital Converter
Analog-to-Digital Converter (ADC) Module he NS9215 ASIC supports a 12-bit successive approximation analog-to-digital converter (ADC). To maximize flexibility, an input pin is provided to apply an external reference voltage, which defines the full scale input range. An analog multiplexer is included to enable the selection of up to eight inputs.
Page 474: Adc Control Block
FIFO overflow is detected. The RX FIFO overflow interrupt should be enabled to detect an overflow. Configure the ADC Configuration register at address 9003 9000 for DMA operation (bit 3 set to 1) and the number of channels but leave bit 31 set to a 0. Hardware Reference NS9215 vref vref_gnd vin_7...
Page 475: Adc Control And Status Registers
Set up the ADC DMA control registers and buffer descriptors (UART channel D). Reset the ADC module by writing a 0 then a 1 to bit 8 in the Module Reset register at address A090 0180. Flush the ADC DMA FIFO by writing a 1 then a 0 to bit 17 in UART Channel D Wrapper Configuration register at address 9002 9000.
Page 476 A N A L O G - T O - D I G I T A L C O N V E R T E R ( A D C ) M O D U L E ADC Configuration register Register ADCEN Register bit Bit(s) Access assignment D30:19 D18:16 D15:5 D02:00 Hardware Reference NS9215 Reserved Reserved Mnemonic Reset ADCEN Reserved INSTAT Interrupt status Indicates the channel processed at the time of the interrupt. Reserved...
Page 477: Adc Clock Configuration Register
A D C C l o c k C o n f i g u r a t i o n r e g i s t e r ................. . Address: 9003_9004 The ADC Clock Configuration register controls the ADC clock generator.
Page 478 ADC Output Registers 0-7 Register Not used Register bit Bit(s) Access assignment D31:12 D11:00 Hardware Reference NS9215 Not used DOUT Mnemonic Reset Description Not used This field must be written to 0. DOUT Provides the output of the ADC for each channel.
Page 479: Electrical Characteristics
Timing his chapter provides the electrical specifications, or timing, integral to the operation of the processor. Timing includes information about DC and AC characteristics, output rise and fall timing, and crystal oscillator specifications. E l e c t r i c a l c h a r a c t e r i s t i c s .
Page 480: Recommended Operating Conditions
CPU / Memory clock 150MHz/75MHz 75 MHz/75MHz 112MHz/56MHz 56MHz/56MHz Sleep Mode, wake on Ethernet Sleep Mode, wake on External IRQ Main Power Down, Battery Draw Hardware Reference NS9215 Symbol (core) Ratings of internal cells Power Total 1.019W Core 0.880W I/O 0.139W Total 0.828W...
Page 481: Dc Electrical Characteristics
D C e l e c t r i c a l c h a r a c t e r i s t i c s ................. . DC characteristics specify the worst-case DC electrical performance of the I/O buffers that are guaranteed over the specified temperature range.
Page 482: Ouputs
A maximum rise and fall time must be met to ensure that reset and edge sensitive inputs are handled correctly. With Digi processors, the maximum is 500 nanoseconds as shown: Hardware Reference NS9215...
Page 483 If an external device driving the reset or edge sensitive input on a Digi processor cannot meet the 500ns maximum rise and fall time requirement, the signal must be buffered with a Schmitt trigger device. Here are sample Schmitt trigger device part...
Page 484: Memory Timing
All four data_mask signals will go low during a read cycle, for both 16-bit and 32-bit transfers. Only one of the clk_out signals is used. Only one of the dy_cs_n signals is used. Hardware Reference NS9215 Unit Notes 1, 2...
Page 485: Sdram Burst Read (16-Bit)
SDRAM burst read (16-bit) pr e a c t c l k _ ou t d a ta< 3 1:1 6 > a d d r N ot e- 1 d a ta _m as k < 3 : 0 > d y _c s _ n<...
Page 486: Sdram Burst Read (16 Bit), Cas Latency = 3
_c s _ n< 3: 0> * ra s _n c a s _n we _n Notes: This is the bank and RAS address. This is the CAS address. Hardware Reference NS9215 r ea d la t la t d- A d- B d -C...
Page 487: Sdram Burst Write (16 Bit)
SDRAM burst write (16 bit) p r e c l k _ o u t d a ta < 3 1 : 0 > a d d r d a ta _ m a s k < 3 : 2 > d a ta _ m a s k <...
Page 488: Sdram Burst Read (32 Bit)
_n c a s _n we _n Notes: This is the bank and RAS address. This is the CAS address. Hardware Reference NS9215 ac t iv e re ad c a s lat M 11 N ote -1...
Page 489: Sdram Burst Read (32 Bit), Cas Latency = 3
SDRAM burst read (32 bit), CAS latency = 3 p re c lk_ ou t d ata < 31: 0> ad dr da ta_ m as k < 3:0 >* d y _c s_ n< 3: 0> * ra s _n c a s _n we _n Notes:...
Page 490: Sdram Burst Write (32-Bit)
_n c as _n w e_n Notes: This is the bank and RAS address. This is the CAS address. Hardware Reference NS9215 ac ti ve w r d-A data-B N ote- 1 N ote- 2 data-C dat a-D...
Page 491: Sdram Load Mode
SDRAM load mode clk_o ut dy_ cs_n<3 :0> * ras_ n cas_ n w e_ n a dd r<11 :0 > www.digiembedded.com op cod e SD L dM d T I M I N G Memory Timing...
Page 492: Sdram Refresh Mode
T I M I N G Memory Timing SDRAM refresh mode clk_o ut dy_ cs0_ n dy_ cs1_ n dy_ cs2_ n dy_ cs3_ n ras_ n cas_ n we_ n Hardware Reference NS9215...
Page 493: Clock Enable Timing
T I M I N G Memory Timing Clock enable timing clk_out clk_en<3:0> SDRAM cycle clk_enable.td www.digiembedded.com...
Page 494: Values In Sram Timing Diagrams
Use this formula to calculate the length of the st_cs_n signal: Tacc + board delay + (optional buffer delays, both address out and data in) + 10ns Hardware Reference NS9215 signals is used. The diagrams show the active low configuration, which can be...
Page 495: Static Ram Read Cycles With 0 Wait States
Static RAM read cycles with 0 wait states c lk _ ou t d ata < 31: 0> ad dr < 27: 0> s t_c s _ n< 3: 0> oe _n by te _lan e< 3: 0> S t ti R A M WTRD = 1 WOEN = 0 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-...
Page 496: Static Ram Asynchronous Page Mode Read, Wtpg = 1
If the PB field is set to 0, the byte_lane signal will always be high during a read cycle. Setting the BMODE (Burst mode) bit D02 in the static memory configuration register allows the static output enable signal to toggle during bursts. Hardware Reference NS9215 N o te- 2 N o te- 2...
Page 497: Static Ram Read Cycle With Configurable Wait States
Static RAM read cycle with configurable wait states clk_ ou t d ata < 31: 0> M 17 ad dr< 27: 0> M 19 N ote -1 st_cs_ n<3: 0> M 27 N ote -1 oe _n M 23 N ote -1 byte _lan e<3: 0>...
Page 498: Static Ram Sequential Write Cycles
During an 8-bit transfer, only one byte_lane signal will go low. Note: If the PB field is set to 0, the byte_lane signals will function as write enable signals and the we_n signal will always be high. Hardware Reference NS9215 M 22 M 22 M 16...
Page 499: Static Ram Write Cycle
Static RAM write cycle clk_ ou t d ata < 31: 0> ad dr< 27: 0> st_cs_ n< 3: 0> we _n byte _lan e< 3: 0> N ot e- 1 byte _lan e[ 3:0 ] a s WE * WTWR = 0 WWEN = 0 During a 32-bit transfer, all four byte_lane signals will go low.
Page 500: Static Write Cycle With Configurable Wait States
If the PB field is set to 0, the byte_lane signals will function as the write enable signals and the we_n signal will always be high. If the PB field is set to 0, the timing for the byte_lane signals is set with the WTWR and WWEN fields. Hardware Reference NS9215 N ote - 1 M 22...
Page 501: Slow Peripheral Acknowledge Timing
The table below describes the values shown in the slow peripheral acknowledge Slow peripheral timing diagrams. acknowledge timing Parm Description clock high to data out valid data out hold time from clock high clock high to address valid address hold time from clock high clock high to st_cs_n low clock high to st_cs_n high clock high to we_n low...
Page 502: Slow Peripheral Acknowledge Read
Slow peripheral acknowledge write clk_out data<31:0> addr<27:0> st_cs_n<3:0> we_n byte_lane<3:0> ta_strb Hardware Reference NS9215 10 0n s M3 2 M2 9 M3 0 50ns 100ns 15 0n s 20 0n s M2 6 M1 8 M2 0...
Page 503: Ethernet Timing
All AC characteristics are measured with 10pF, unless otherwise noted. Ethernet timing The table below describes the values shown in the Ethernet timing diagrams. Parm Description MII tx_clk to txd, tx_en, tx_er MII rxd, rx_en, rx_er setup to rx_clk rising MII rxd, rx_en, rx_er hold from rx_clk rising mdio (input) setup to mdc rising mdio (input) hold from mdc rising...
Page 504: I 2 C Timing
DATA hold time iic_sda to iic_scl DATA setup tim iic_scl to iic_sda STA iic_scl to iic_sda STOP setup time ii c_s da ii c_ scl Hardware Reference NS9215 Standard Mode C timing diagram. Fast Mode Unit µ...
Page 505: Spi Timing
All AC characteristics are measured with 10pF, unless otherwise noted. SPI Timing The next table describes the values shown in the LCD timing diagrams. Parm Description SPI master parameters SPI enable low setup to first SPI CLK out rising SPI enable low setup to first SPI CLK out falling SPI data in setup to SPI CLK out rising SPI data in hold from SPI CLK out rising...
Page 506 ± 10% duty cycle skew. = 5pf for all outputs. load SPI data order can be reversed such that LSB is first. Use the BITORDR bit in Serial Channel B/A/C/D Control Register A. Hardware Reference NS9215 Unit SP26*40% SP26*60% 0,1,2,...
Page 507: Spi Master Mode 0 And 1: 2-Byte Transfer
SPI master mode 0 and 1: 2-byte transfer SPI CLK Ou t (M ode 0) SPI CLK Ou t (M ode 1) SPI Enable SPI Data Out S PI Data In M SB Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel B/A/C/D Control Register A.
Page 508: Spi Slave Mode 0 And 1: 2-Byte Transfer
SPI D ata In M SB Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel B/A/C/D Control Register A. Hardware Reference NS9215 SP 3 S P1 3 S P1 3 S P5...
Page 509: Reset And Hardware Strapping Timing
R e s e t a n d h a r d w a r e s t r a p p i n g t i m i n g ................. . All AC characteristics are measured with 10pF, unless otherwise noted.
Page 510: Jtag Timing
Maximum tck rate is 10 MHz. is an asynchronous output, driven off of the CPU clock. rtck_out is an asynchronous input. trst_n Hardware Reference NS9215 Description tms (input) setup to tck rising tms (input) hold to tck rising tdi (input) setup to tck rising...
Page 511: Clock Timing
C l o c k t i m i n g ................. . All AC characteristics are measured with 10pF, unless otherwise noted.
Page 512 T I M I N G Clock timing Hardware Reference NS9215...
Page 513: Package
Packaging elow is the processor package, 265 LF-XBGA. Diagrams that follow show the processor dimensions: top, bottom, and side views. P a c k a g e ................. .
Page 514: Processor Dimensions
................. . Hardware Reference NS9215...
Page 515 P A C K A G I N G Processor Dimensions www.digiembedded.com...
Page 516 P A C K A G I N G Processor Dimensions Hardware Reference NS9215...
Page 517: Change Log
Change log he following changes were made since the last revision of this document. R e v i s i o n B ................. . Modified ADC data in the POR table.

Digi NS9215 Hardware Reference Manual

Chapter 9 : I / O H U B M O D U L

Chapter 1 5 : a N a L O G - T O - D I G I T a L C O N V E R T E R ( a D C ) M O D U L

Chapter 1 2 : S E R I a L C O N T R O L M O D U L E : S P

Chapter 1 1 : S E R I a L C O N T R O L M O D U L E : H D L

Chapter 1 0 : S E R I a L C O N T R O L M O D U L E : U a R

Chapter 8 : a E S D a T a E N C R y P T I O N / D E C R y P T I O N M O D U L

Chapter 1 3 : I 2 C M a S T E R / S L a V E I N T E R F a C

Chapter 1 : P I N O U T ( 2 6 5 )

Chapter 2 : I / O C O N T R O L M O D U L E

Chapter 3 : Working with the CPU

Chapter 4 : System Control Module

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