Test Description - Intel F-Tile SDI II Agilex User Manual

Figure 21. Duplex Mode Simulation Testbench Block Diagram
Top
SDI Du Sys
F-tile PMA/
FEC Direct
PHY IP (TX)
Note: Refer to
connections.
Table 11. Testbench Components
Component
Testbench Control
TX checker
RX checker

2.4.2. Test Description

The simulation only checks for the assertion of
transceiver reconfiguration triggered after every video standard switching.
® ™
F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
28
F-tile PMA/
FEC Direct
PHY IP (RX)
SDI F-tile
PHY Adapter
Clocking Scheme on page 22 for the Reference and System PLL Clocks IP
This block controls the test sequence of the simulation and generates the necessary stimulus
signals to the TX and video pattern generator blocks.
This checker verifies if the TX serial data contains a valid TRS signal.
This checker detects the
number of transceiver reconfigurations performed versus the expected number.
2. Design Example Detailed Description
Du Top
SDI II
(Duplex)
Parallel Data
Serial Data
Description
from the RX protocol and compares the actual
trs_locked signal
trs_locked
710496 | 2022.01.28
Video Pattern
Generator
Testbench
Control
TX Checker
RX Checker
Reference
and System
PLL Clocks IP
Control/Status
signal and the number of
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