Inbound Pci Locks; Atomic Writes; Atomic Reads; Locks With Agp Non-Coherent Traffic - Intel 460GX Software Developer’s Manual

AGP LOCKS
There is no LOCK signal on the AGP bus. However, legacy code that issues read-modify-write
(RMW) transactions could still be converted for use with an AGP device. The GXB will attempt to
establish a "pseudo-lock" to cover such an event. However, there is still a deadlock case within the
AGP controller that the GXB can not address. This case is covered in a "special design
considerations" section of the AGP specification.
The deadlock occurs when the device internally posts an inbound write after the first read
completes in a "R-R-W-W" locked sequence. The specification requires that the AGP master
resolve the problem in either software or hardware:
•
Software must prevent the device driver from accessing internal registers with misaligned
reads while there are posted writes in the PCI interface. This works if the device never posts
writes, implements a unified interface (i.e.: no "internally posted" writes), or disallows
misaligned read access (no multi-word registers).
•
Hardware allows the read to proceed even in the presence of the posted write. Technically this
is a violation of protocol, but the master is at liberty to insure that internal status doesn't get
updated on behalf of the "posted" write until that data actually leaves the part.
3.6.2

Inbound PCI Locks

The 460GX chipset does not support inbound locks.
3.6.3

Atomic Writes

Some system bus operations such as Write 8 bytes, Write 16 bytes and Write 32 bytes, are
indivisible operations on the system bus. However, since the PCI protocol allows target device to
disconnect at any point in a transfer sequence, these operations are not indivisible on the PCI bus.
Furthermore, these accesses cannot be locked because PCI specification allows use of locked
cycles only if the first transaction of the locked operation is a read. Therefore software must not
rely upon atomicity of system bus write transactions which are greater than 32 bits or Dword
misaligned once they are translated to the PCI bus.
3.6.4

Atomic Reads

The system bus memory read operations to PCI can request more than 32-bits of data (i.e. 8 byte,
16 byte and 32 byte). The problem of indivisibility of operations is very critical for this type of
transaction. The PXB does NOT Lock multi-cycle reads to guarantee atomicity. Note that
ATOMICITY of Host-PCI reads which are greater than 32 bits or are Dword misaligned is NOT
GUARANTEED.
The PXB can accept inbound reads and writes while an outbound read or write is in a partially
completed state.
3.6.5

Locks with AGP Non-coherent Traffic

AGP has a non-coherent stream that does not go over the system bus. Therefore processor locks,
whether established to memory or I/O, do not prevent the non-coherent AGP accesses from
occurring. If a processor reads a location in memory with a locked read, and then writes the same
Intel® 460GX Chipset Software Developer's Manual
System Architecture
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