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MICRO-ARCHITECTURE OVERVIEW
BTB0
BTB1
IFU0
IFU1
IFU2
ID0
ID1
RAT
ROB
Rd
Figure 2-8. Out of Order Core and Retirement Pipeline
2-10
IFU:
Instruction Cache Unit
IFU1: In this stage, 16-byte instruction packets are fetched.
The packets are aligned on 16-byte boundaries.
IFU2: Instruction Pre-decode: double buffered: 16-byte
packets aligned on any boundary.
ID0:
Instruction Decode
ID1:
Decode 1 stage: decoder limits
= at most 3 macro-instructions per cycle
= at most 6 µops (411) per cycle
= at most 3 µops per cycle exit the queue
= instructions ≤7 bytes in length
RAT: Register Allocation
Decode IP relative branches
= at most one per cycle
= Branch information sent to BTB0 pipe stage
Rename = partial and flag stalls
Allocate resources = the pipeline stalls if the
ROB is full
ROB Re-order Buffer Read
= at most 2 completed physical registers reads
per cycle
001049
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