Sftr (Shift Right) - IDEC FC4A-C10R2 User Manual

SFTR (Shift Right)

SFTR(W)
*****
When bits to shift = 1
Before shift:
After shift:
Applicable CPU Modules
FC4A-C10R2/C FC4A-C16R2/C
X
Valid Operands
Operand
S1 (Source 1)
bits
For the valid operand number range, see pages 6-1 and 6-2.
▲
Internal relays M0 through M1277 can be designated as S1. Special internal relays cannot be designated as S1.
The quantity of bits to shift can be 1 through 15.
Since the SFTR instruction is executed in each scan while input is on, a pulse input from a SOTU or SOTD instruction
should be used as required.
Valid Data Types
W (word) I (integer)
X —
Example: SFTR
MOV(W) S1 –
M8120
SFTR(W)
SOTU
I0
Bits to shift = 2
Before shift: D20 = 29
After first shift: D20 = 7
After second shift: D20 = 1
S1 → CY
S1 bits
When input is on, 16-bit data of the designated source operand S1 is shifted to
**
the right by the quantity of bits designated by operand bits.
The result is set to the source operand S1, and the last bit status shifted out is
set to a carry (special internal relay M8003). Zeros are set to the MSB.
MSB
0 1 0 0 1
MSB
0 1 0 0
FC4A-C24R2/C
X X
Function
Data for bit shift
Quantity of bits to shift
When a bit operand such as Q (output), M (internal relay), or R (shift register) is designated
as the source, 16 points are used.
When a word operand such as D (data register) is designated as the source, 1 point is used.
D1 – REP
29 D10
S1 bits
D10 2
MSB
0 0
MSB
0 0
MSB
« FC4A M
S1
1 0 1 0 1 1 1 0
Shift to the right
S1
1 1 0 1 0 1 1 1
FC4A-D20K3/S3
X
I
—
— — — — — — —
M8120 is the initialize pulse special internal relay.
When the CPU starts operation, the MOV (move) instruction sets 29 to
data register D10.
Each time input I0 is turned on, 16-bit data of data register D10 is shifted
to the right by 2 bits as designated by operand bits. The last bit status
shifted out is set to a carry (special internal relay M8003). Zeros are set
to the MSB.
D10
0 0 0 0 0 0 0 0 0
Shift to the right
D10
0 0 0 0 0 0 0 0
D10
0 0 0 0 0 0 0 0
S U ' M
ICRO MART SER S ANUAL
13: S / R
HIFT OTATE
LSB CY
0 1 1 0
M8003
LSB CY
0 0 1 1 0
M8003
FC4A-D20RK1/RS1 & FC4A-D40K3/S3
Q M R T C D
▲
X X — — X
LSB
0 0 1 1 1 0 1
LSB
0 0 0 0 0 1 1 1
LSB
0 0 0 0 0 0 0 1
»
I
NSTRUCTIONS
X
Constant Repeat
— —
1-15 —
CY
M8003
CY
0
M8003
CY
1
M8003
13-3