IDEC FC4A-C10R2 User Manual page 204

7: B I
ASIC NSTRUCTIONS
Reverse Shift Register (SFRN)
For reverse shifting, use the SFRN instruction. When SFRN instructions are programmed, two addresses are always
required. The SFRN instructions are entered, followed by a shift register number selected from appropriate operand num-
bers. The shift register number corresponds to the lowest bit number in a string. The number of bits is the second required
address after the SFRN instructions.
The SFRN instruction requires three inputs. The reverse shift register circuit must be programmed in the following order:
reset input, pulse input, data input, and the SFRN instruction, followed by the last bit and the number of bits.
Ladder Diagram
Last Bit
Reset
SFRN R20
7
I0
Pulse
# of Bits
I1
Data
I2
R21
R23
R25
• The last bit status output can be programmed directly after the SFRN instruction. In this example, the status of bit R20
is read to output Q0.
• Each bit can be loaded using the LOD R# instructions.
• For details of reset, pulse, and data inputs, see page 7-18.
Structural Diagram
Shift Direction
R20 R21 R22 R23 R24 R25 R26
Last Bit: R20
Note: Output is initiated only for those bits highlighted in bold print.
Note: When power is turned off, the statuses of all shift register bits are normally cleared. It is also possible to maintain
the statuses of shift register bits by using the Function Area Settings as required. See page 5-4.
• For restrictions on ladder programming of shift register instructions, see page 29-22.
Caution
7-20
Q0
CPU Type
Last Bit
# of Bits
Q1
Q2
Q3
Reset
I0
Data
I2
Pulse
I1
# of Bits: 7
« FC4A M
All-in-One 10-I/O
R0 to R63 R0 to R127
1 to 64
S U ' M
ICRO MART SER S ANUAL
Program List
Instruction
LOD
Others
LOD
LOD
SFRN
1 to 128
OUT
LOD
OUT
LOD
OUT
LOD
OUT
»
Data
I0
I1
I2
R20
7
Q0
R21
Q1
R23
Q2
R25
Q3