Basic Instruction List - IDEC FC4A-C10R2 User Manual

7: B I
ASIC
Introduction
This chapter describes programming of the basic instructions, available operands, and sample programs.
All basic instructions are available on all

Basic Instruction List

Symbol
AND And
AND LOD And Load
ANDN And Not
BPP Bit Pop
BPS Bit Push
BRD Bit Read
CC= Counter Comparison (=)
CC≥ Counter Comparison (≥)
CDP Dual Pulse Reversible Counter
CNT Adding Counter
Up/Down Selection
CUD
Reversible Counter
DC= Data Register Comparison (=)
DC≥ Data Register Comparison (≥)
END End
JEND Jump End
JMP Jump
LOD Load
LODN Load Not
MCR Master Control Reset
MCS Master Control Set
OR Or
OR LOD Or Load
ORN Or Not
OUT Output
OUTN Output Not
RST Reset
SET Set
SFR Shift Register
SFRN Shift Register Not
SOTD Single Output Down
SOTU Single Output Up
TIM 100-ms Timer
TMH 10-ms Timer
TML 1-sec Timer
TMS 1-ms Timer
NSTRUCTIONS
MicroSmart
Name
Series connection of NO contact
Series connection of circuit blocks
Series connection of NC contact
Restores the result of bit logical operation which was
saved temporarily
Saves the result of bit logical operation temporarily
Reads the result of bit logical operation which was
saved temporarily
Equal to comparison of counter current value
Greater than or equal to comparison of counter current
value
Dual pulse reversible counter (0 to 65535)
Adding counter (0 to 65535)
Up/down selection reversible counter (0 to 65535)
Equal to comparison of data register value
Greater than or equal to comparison of data register
value
Ends a program
Ends a jump instruction
Jumps a designated program area
Stores intermediate results and reads contact status
Stores intermediate results and reads inverted contact
status
Ends a master control
Starts a master control
Parallel connection of NO contact
Parallel connection of circuit blocks
Parallel connection of NC contact
Outputs the result of bit logical operation
Outputs the inverted result of bit logical operation
Resets output, internal relay, or shift register bit
Sets output, internal relay, or shift register bit
Forward shift register
Reverse shift register
Falling-edge differentiation output
Rising-edge differentiation output
Subtracting 100-ms timer (0 to 6553.5 sec)
Subtracting 10-ms timer (0 to 655.35 sec)
Subtracting 1-sec timer (0 to 65535 sec)
Subtracting 1-ms timer (0 to 65.535 sec)
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