IDEC FC4A-C10R2 User Manual page 128

5: S F
PECIAL UNCTIONS
Special Data Registers for Single-phase High-speed Counters (All-in-One Type CPU Modules)
Description
High-speed Counter Current Value
High-speed Counter Preset Value
Single-phase High-speed Counter Specifications (All-in-One Type CPU Modules)
Maximum Counting Frequency
Counting Range
Operation Mode
Gate Control
Current Value Reset
Status Relays
Comparison Output
High-speed Counters on Slim Type CPU Modules
Slim type CPU modules have four high-speed counters; HSC1 through HSC4. HSC1 and HSC4 can be used as a two-
phase or single-phase high-speed counter. HSC2 and HSC3 are single-phase high-speed counters. All high-speed counter
functions are selected using the Function Area Settings in
High-speed Counter Operation Modes and Input Terminals (Slim Type CPU Modules)
High-speed Counter No.
Input Terminal
Two-phase
High-speed Counter
Single-phase
High-speed Counter
For wiring high-speed counter input signals, use twisted-pair shielded cables.
Two-phase High-speed Counters HSC1 and HSC4 (Slim Type CPU Modules)
Two-phase high-speed counter HSC1 or HSC4 operates in the rotary encoder mode, and counts up or down input pulses to
input terminals I0 or I6 (phase A) and I1 or I7 (phase B), respectively. When the current value overflows 65535 or under-
flows 0, a designated comparison output turns on. Any output terminal available on the CPU module can be designated as
a comparison output. When input I2 or I5 (reset input) is turned on, the current value is reset to a predetermined reset
value, and the two-phase high-speed counter counts subsequent input pulses starting at the reset value.
Two special data registers and six special internal relays are assigned to control and monitor each two-phase high-speed
counter operation. The current value is stored in data register D8045 or D8051(current value) and is updated every scan.
The value stored in D8046 or D8052 (reset value) is used as a reset value. When a high-speed counter reset input (I2/I5 or
M8032/M8046) is turned on, the current value in D8045 or D8051 is reset to the value stored in D8046 or D8052.
The two-phase high-speed counter is enabled while gate input special internal relay M8031 or M8045 is on and is disabled
while M8031 or M8045 is off. When current value overflow or underflow occurs while counting up or down, special inter-
nal relay M8131/M8136 or M8132/M8137 turns on in the next scan, respectively. At this point, the D8045 or D8051 cur-
rent value is reset to the D8046 or D8052 reset value for the subsequent counting cycle. When comparison output reset
special internal relay M8030 or M8044 is turned on, the designated comparison output is turned off. When reset input I2 or
I5 is turned on to reset the current value, reset status special internal relay M8130 or M8135 turns on in the next scan.
When reset input special internal relay M8032 or M8046 is turned on, M8130 or M8135 does not turn on. See page 5-13.
Note: When using input I2 or I5 as a phase Z input, set 0 to reset value special data register D8046 or D8052, respectively.
5-8
High-speed Counter No.
HSC1 HSC2
D8045 D8047
D8046 D8048
HSC1:
HSC2 through HSC4:
0 to 65535 (16 bits)
Adding counter
Enable/disable counting
Current value is reset to 0 when the current value reaches the preset value or when
reset input I2 (HSC1 only) or a reset input special internal relay is turned on.
Special internal relays for indicating high-speed counter statuses.
Any output number available on the CPU module can be designated as a comparison
output which turns on when the current value reaches the preset value.
Output numbers on expansion output or mixed I/O modules cannot be designated as a
comparison output.
HSC1
I0 I1
Reset Input
Phase A Phase B
(Phase Z)
Pulse
— Reset Input
Input
« FC4A M
ICRO
HSC3 HSC4
D8049 D8051
D8050 D8052
20 kHz
5 kHz
.
WindLDR
HSC2 HSC3
I2 I3 I4
— —
Pulse Pulse
Input Input
S U ' M »
MART SER S ANUAL
Updated Read/Write
Every scan Read only
—
HSC4
I5 I6
Reset Input
Phase A
(Phase Z)
Reset Input —
R/W
I7
Phase B
Pulse
Input