IDEC FC4A-C10R2 User Manual page 203

Forward Shift Register (SFR), continued
Ladder Diagram
Reset
SFR R0
4
I0
Pulse
I1
Data
I2
R0 Q0
R1 Q1
R2 Q2
R3 Q3
Ladder Diagram
Reset
SFR R0
4
I1
Pulse
I2
Data
I3
R0
R1
Setting and Resetting Shift Register Bits
S
I0 R0
R
I1 R3
Program List
Instruction
LOD
LOD
LOD
SFR
LOD
OUT
LOD
OUT
LOD
OUT
LOD
OUT
Timing Chart
Reset Input I0
Pulse Input I1
Data Input I2
R0/Q0
R1/Q1
R2/Q2
R3/Q3
Program List
Q3
Q0
• The last bit status output can be programmed directly after
Q1
• Each bit can be loaded using the LOD R# instruction.
• Any shift register bit can be turned on using the SET instruction.
• Any shift register bit can be turned off using the RST instruction.
• The SET or RST instruction is actuated by any input condition.
« FC4A M
ICRO
Data
I0
I1
I2
R0
4
R0
Q0
R1
Q1
R2
Q2
R3
Q3
ON
OFF
One scan or more is required
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Instruction Data
LOD I1
I2
LOD
LOD I3
SFR R0
4
OUT Q3
LOD R0
OUT Q0
LOD R1
OUT Q1
the SFR instruction. In this example, the status of bit R3 is
read to output Q3.
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MART SER S ANUAL
7: B I
ASIC NSTRUCTIONS
7-19