V832 To S1D13505 Interface; Hardware Description - Epson S1D13505 Technical Manual

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4 V832 to S1D13505 Interface

4.1 Hardware Description

NEC V832
LLBEN
LUBEN
IORD
IOWR
CSn
READY
A[25:1]
D[15:0]
SDCLKOUT
VDD_O
VDD_I
Note:
When connecting the S1D13505 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
S1D13505
X23A-G-012-02
The NEC V832 microprocessor features configurable chip select lines which can easily be
used for an external LCD controller. It provides all the necessary internal address decoding
and control signals required by the S1D13505.
The diagram below shows a typical implementation utilizing the S1D13505.
+3.3V
+2.5V
Figure 4-1: NEC V832 to S1D13505 Configuration Schematic
Note
For pin mapping see Table 3-1:, "Host Bus Interface Pin Mapping," on page 10.
Pull-up
System RESET
A21
Epson Research and Development
Vancouver Design Center
S1D13505
RD/WR#
WE1#
RD#
WE0#
CS#
WAIT#
RESET#
M/R#
AB[20:1]
DB[15:0]
BUSCLK
V (+3.3V)
DD
BS#
V
DD
AB0
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/05