S1D13505 Host Bus Interface; Pr31500/Pr31700 Host Bus Interface Pin Mapping - Epson S1D13505 Technical Manual

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3 S1D13505 Host Bus Interface

Note

3.1 PR31500/PR31700 Host Bus Interface Pin Mapping

Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/05
The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the
PR31500/PR31700 microprocessor.
The PR31500/PR31700 host bus interface is selected by the S1D13505 on the rising edge
of RESET#. After releasing reset, the bus interface signals assume their selected
configuration. For details on S1D13505 configuration, see Section 4.2, "S1D13505 Config-
uration" on page 12.
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
The following table shows the function of each host bus interface signal.
Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping
S1D13505 Pin Name
AB20
AB19
AB18
AB17
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
Philips PR31500/PR31700
ALE
/CARDREG
/CARDIORD
/CARDIOWR
V
DD
A[12:0]
D[23:16]
D[31:24]
/CARDxCSH
V
DD
V
DD
DCLKOUT
V
DD
/CARDxCSL
/RD
/WE
/CARDxWAIT
RESET#
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S1D13505
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