Edo-Dram Cas Before Ras Refresh Timing; Table 7-16: Edo-Dram Cas Before Ras Refresh Timing; Figure 7-16: Edo-Dram Cas Before Ras Refresh Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Page 66

7.3.2 EDO-DRAM CAS Before RAS Refresh Timing

Symbol
t1 Internal memory clock period
RAS# precharge time (REG[22h] bits 3-2 = 00)
t2 RAS# precharge time (REG[22h] bits 3-2 = 01)
RAS# precharge time (REG[22h] bits 3-2 = 10)
RAS# pulse width (REG[22h] bit 6-5 = 00 and bits 3-2
= 00)
RAS# pulse width (REG[22h] bit 6-5 = 00 and bits 3-2
= 01)
RAS# pulse width (REG[22h] bit 6-5 = 00 and bits 3-2
= 10)
RAS# pulse width (REG[22h] bit 6-5 = 01 and bits 3-2
= 00)
RAS# pulse width (REG[22h] bit 6-5 = 01 and bits 3-2
t3
= 01)
RAS# pulse width (REG[22h] bit 6-5 = 01 and bits 3-2
= 10)
RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2
= 00)
RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2
= 01)
RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2
= 10)
t4 CAS# pulse width
CAS# setup time (REG[22h] bits 3-2 = 00 or 10)
t5
CAS# setup time (REG[22h] bits 3-2 = 01)
S1D13505
X23A-A-001-14
t1
Memory
Clock
t2
RAS#
t4
CAS#

Figure 7-16: EDO-DRAM CAS Before RAS Refresh Timing

Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing

Parameter
t3
t5
t6
Min
25
2t1 - 3
1.45t1 - 3
1t1 - 3
3 t1 - 3
3.45 t1 - 3
4 t1 - 3
2 t1 - 3
2.45 t1 - 3
3 t1 - 3
1 t1 - 3
1.45 t1 - 3
2 t1 - 3
t2
0.45 t1 - 3
1 t1 - 3
Epson Research and Development

Vancouver Design Center

Max Units
Hardware Functional Specification
Issue Date: 01/02/02
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns