Page 2
Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products.
Page 3
Configuration of product number DEVICES 15722 Packing specifications Specifications Shape (D : Chip, T:TCP, F:QFP) Model number Model name (D : LCD Driver) Product classification (S1:Semiconductors)
1. DESCRIPTION 1. DESCRIPTION The S1D15722 series is a MLS drive system dot matrix LCD driver that can be directly connected to the microcomputer bus. An 8-bit parallel or serial display data sent from the microcomputer is stored in the built-in display data RAM and LCD drive signal is generated independently of the microcomputer.
(Internal logic is operated by V LCD drive power supply: V = 15V to 25V = GND) • Wide temperature range: - 40 to +90°C • CMOS Process • Shipping form: bare chip • No anti-radiation and light resistance design EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
5.5/13 · V 5/12 · V 4.5/11 · V 4/10 · V 3.5/9 · V 3/8 · V 4.5/13 · V 4/12 · V 3.5/11 · V 3/10 · V 2.5/9 · V 2/8 · V S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
When P/S = LOW, D0 to D7 are Hi-Z. For D0 to D7, it may be set to HIGH, LOW or open. However, set RD (E) and WR (R/ W) to HIGH or LOW. When serial interface is selected, read status is enabled, but read display data RAM is not enabled. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Display clock input/output pin. Sets as shown in the table below depending on the state of M/S and CLS. HIGH Output HIGH Input HIGH Input Input To use this IC on master/slave, connect each CL pin. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Number of Pin name Description pins TEST Pin for testing IC chip. Set to LOW. TEST2 Pin for testing IC chip. Set to open. TEST3 to Pin for testing IC chip. Set to open. TEST17 EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
However, it should be noted that the CS signal is handled differently from the time of serial data input. Read from display data RAM is not enabled. Signal chart of serial interface is shown in Fig.6.1. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Since this IC is accessed as a kind of pipeline processing between LSIs via bus holder coming with internal data bus, wait time is not necessary if the cycle time is satisfied, enabling high-speed data transmission. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 20
Write command BUS Holder Write Signal Read DATA Dummy Read command Read Signal Column Address Preset Increment Bus Holder Read command code Dummy Read Data Read Data Read Fig.6.2 Read Sequence of Display Data RAM S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Fig.6.4, higher degree of freedom is achieved in configuring display with less constraints on display data transfer if the S1D15722 series is used for the multi-chip. Read/write from MPU to RAM is performed via I/O buffer, which is controlled independently of liquid crystal drive RAM.
The display start line address is set every four lines of display. Dynamically changing the line address using the set display start line command enables screen scrolling and page turning. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
The display data latch circuit is a latch for temporarily storing data to be output to the liquid crystal drive circuit from the display data RAM. Since the display normal/inverted, display ON/OFF, and display full lighting ON/OFF commands control data in this latch, data in the display data RAM will not change. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
This circuit detects specific error modes. It does not support all command registers. For command registers to be supported and expanded information, see 7.1 Command Description (30) Read Status. The initial state after resetting is ERR = HIGH. This function is enabled after resetting. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
(Scanning start position: COM91) ( COM(47,46,45,44) ( COM(139,138,137,136) (··· - Invert scan direction ( COM(3,2,1,0) ( COM( (95,94,93,92) * Four lines in parentheses ( ) indicate those of COM to be selected at a time. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 28
(Scan start position: COM91) scanning direction scanning direction COM0 COM92 COM0 COM92 chip bottom view chip bottom view COM91 COM183 COM91 COM183 Fig. 6.7 Relationship between Select Common Output Status Command and LCD Panel Connection S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
To control liquid crystal drive voltage with higher accuracy, configure the system which can reduce variations in output voltage by allowing the MPU to give the feedback of values of the output voltage sampled under certain temperature and store them as reference voltage. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
V relationship between the IC’s board potential and the system ground’s potential. to MV generating circuit generating circuit IC’s board potential ∆V=ΣI×R ΣI System ground Fig.6.8 Influence of Resistance R between System Ground and V S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 31
• Minimize the impact caused by the IC’s external circuits by leaving the system to be used under certain temperature and allowing the system to store the SVD2 voltage measured while operating the system as the reference voltage. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
When using the external power supply for liquid crystal drive, do not supply ____ external power but set high impedance during the pin RES = LOW to prevent shorting in the external power supply and V and apply the specified voltage after canceling reset. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
RAM. At this time the contents of the display data RAM are held. In combination with the invert the display command, all-white display is also available. Setting State of normal display Full display lighting ____ * After resetting by the RES pin, the full display lighting is set to OFF. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 34
The display start line address can be set every four lines of display. The address range that can be specified in the 4-gray scale display in the display mode differs from that in the binary display. Relationship between the register value with the set register and line address is shown below. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 35
Note: Register setting at (1, 0, 1, 1, 1, 0, 0) or higher is not allowed. Sequence of setting display start line Set display start line/set mode Set register Set display start line/cancel mode End change? Setting completed Fig.7.1 Sequence of Setting Display Start Line EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 36
↓ ↓ ____ Note: After resetting by the RES pin, the address is set to the column 00H. Note: Register setting at (1, 1, 1, 0, 0, 0, 0, 0) or higher is not allowed. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 37
For more information, see 6.2.3 Page Address Circuit/Column Address Circuit in FUNCTIONAL DESCRIPTION. Setting Normal Reversal _______ Note: After resetting by the RES pin, the direction is set to normal of setting the column address. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 38
Relationship between the register value with set register and display mode is shown below. Display mode 4-gray scale display Binary display ____ Note: After resetting by the RES pin, the display is set to 4-gray scale. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 39
Note: An asterisk (*) denotes invalid bit. Relationship between the register value with the set register and pallet is shown below. Pallet Pallet 0 Pallet 1 ____ Note: After resetting by the RES pin, the number is set to Pallet 0. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 40
Number of display lines ↓ ↓ ____ Note: After resetting by the RES pin, the number is set to 184 lines. Note: Register setting at (1, 0, 1, 1, 1, 0) or higher is not allowed. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 41
88 lines appears from COM132. COM183 is followed by COM0. COM0 COM0 46 line COM4 COM45 88 line COM91 COM132 52 line COM183 COM183 Setup example 1 Setup example 2 Fig.7.2 Image of Correspondence between COM Output and the Number of Display Lines EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 42
The page address set command and column address set command. Sequence of cursor display Set page address Set column address Read-modify-write Dummy read Data read Data processing Data write End change? Fig.7.3 Sequence of Cursor Display S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 43
This command sets the dividing ratio of the internal clock f to the built-in oscillation circuit frequency f Enabled only when the built-in oscillation circuit is ON. Command Set mode Set register Note: An asterisk (*) denotes invalid bit. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 44
RES pin and set to discharge OFF after clearing reset. This command short-circuits each liquid crystal drive voltages to V with switching elements. Be sure to execute this command after turning off the external power supply to avoid possible breakdown caused by over current. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 45
It is recommended to quit the power saving-state, goes power-saving OFF after turing the external power circuit ON and stabilized it. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 46
So the register P0 will be set to HIGH after resetting by a pin. Therefore, in normal operation sequence, the above five commands must be set in the register again before executing read status. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 47
This function reduces the AC drive defledction therefore reduce the dark / light stripes. Dispersion / Non-dispersion drive This function is controlled by parameter P3. The S1D15722 uses 4 line MLS drive method, and common EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 48
Command for IC chip testing. Do not use. If this command is executed, the IC goes into test mode. If the IC goes into test mode by mistake, execute the NOP command to clear test mode. Command Set mode S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
(23) Power save ON/OFF Power save 0: OFF, 1: ON Outputs the result of detecting bit error (24) Read status to ERR bus Temperature sensor Operation of the temperature sensor (25) ON/OFF 0: OFF, 1: ON EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 50
1 P3/ 0: Dispersion, 1: Non-dispersion (27) NOP 1 Command for Non-Operation. Command for testing IC chip. (28) TEST1 (Prohibit) Command for testing IC chip. (29) TEST2 (Prohibit) 1 Command for testing IC chip. (30) TEST3 (Prohibit) S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
(25) Temperature seosor ON/OFF (26) TEST1 set <When external clock using,> Input clock to CL pin Supply LCD voltages externally *4 End of initial setting Numbers in parentheses correspond to those in the item of command description. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 52
*2 The contents of the display data RAM are undefined after completion of initial setting. Write data all the display data RAMs to be used for display. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 53
*4: When the IC chip goes into power-saving mode, the discharge OFF command can be used to exit. *5: When the IC chip goes into read-modify-write mode, the end command can be used to exit. *6: When the IC chip goes into test mode, the NOP command can be used to exit. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Page 54
*3: Set to the number of frame frequency that won’t cause display problem such as a flicker. *4: Set to the number of n line inversions that won’t cause display problem such as a flicker. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 55
SEG and COM pins, which could cause display problem. Be sure to follow the above power supply OFF sequence. *1: The threshold voltage of the LCD panel 1[V] serves as an index. Prevent V and V from becoming high impedance during discharge (reset). EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
2: The use of IC exceeding the absolute maximum rating can cause permanent damage to the IC. During normal operation, electrical characteristics conditions should be observed. Failure to do so can cause malfunction of the IC and have adverse effect on the reliability of IC. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
*9 For relationship between the oscillation frequency and the frame frequency, see Table 9.7. The internal oscillation items indicates manufacturing variations in the built-in oscillation circuit while the external input item indicates the maximum operability. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Unit Remarks 1/184 Duty 1/132 Duty magnification Typ. Max. Typ. Max. µ A Table 9.3 Display Heavy Load Pattern Standard value Booster voltage Unit Remarks 1/184Duty 1/132 Duty magnification Typ. Max. Typ. Max. µ A S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Applicable when no access is made from MPU. 9.2 Current Consumption in the Power-saving Mode • V = 5V, T = 25°C Table 9.6 Standard value Item Symbol Conditions Unit Remarks Min. Typ. Max. µA Sleep state = HIGH DDS1 = LOW EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
• V = 5.0 V, Display mode binary, = 100 Hz, no n line inversion, 1/13 bias, non-dispersion drive, T 25°C. =5V, V =20V Display heavy load =5V, V =20V Display all white Display Line Fig.9.2 S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
= 100 Hz, no n line inversion, built-in power supply OFF, 1/13 bias, non-dispersion drive, display ON, T = 25°C. 0.001 0.01 f [MH z ] Fig.9.3 9.3.3 Operating Voltage Rage of V Series and V Series Operation voltage range of and V Fig.9.4 EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
• 2 CL clock correspond to 1 common line scanned period. • Frame frequency indicates the frequency that rewrites 1 frame, but it does not indicate a signal (= a cycle of AC drive) from the FR pin. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
It is applied not to connect capacitance to SVD2 pin. Be sure to sample the output voltage after a fixed wait time or longer. *16: Include operating current of built-in V generating circuit. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
10. TIMING CHARACTERISTICS 10. TIMING CHARACTERISTICS 10.1 System Bus Read/Write Characteristics 1 (80 Series MPU) WCYC8 WCYC8C RCYC8 RCYC8C CCLR CCLW CCHR CCLRC CCLWC CCHRC CCHWC DH8C D0 to D7 (Write) ACC8 D0 to D7 (Read) Fig.10.1 S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 65
CS is at LOW and WR and RD are at the CCLW CCLR LOW level. *5. All timings are stipulated on the basis of 20% and 80% of V EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
10. TIMING CHARACTERISTICS 10.2 System Bus Read/Write Characteristics 2 (68 Series MPU) WCYC6 WCYC6C RCYC6 RCYC6C EWHR EWHW EWLR EWLW EWHRC EWHWC EWLRC EWLWC DH6C D0 to D7 (Write) ACC6 ACC6C OH6C D0 to D7 (Read) Fig.10.2 S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
Page 67
EWHR are stipulated by the overlap period when CS is at LOW and E is at the HIGH level. EWHW EWHR *5. All timings are stipulated on the basis of 20% and 80% of V EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
ACCS Output disable time (Read) *1. The rising and trailing times ( ) of the input signal are below 15 ns. *2. All timings are stipulated on the basis of 20% and 80% of V S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
*1: All timings are stipulated on the basis of 20% and 80% of V WHCL WLCL × × *2: The CL duty ratio is stipulated by *3 A signal beyond the specification has no problem for the functionality, but always WLCL WHCL should be kept. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
ON beforehand. T o set the temperature sensor to ON after stopping access from MPU, provide a given output voltage setup time. *3: Wait time until access from MPU can be started after completion of SVD2 sampling by MPU. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
A1 to A15 Decoder D0 to D7 D0 to D7 ____ ____ ______ RESET Fig.11.2 68 Series (3) Serial Interface Decoder A1 to A7 Port 1 Port 2 ____ ____ ______ RESET Fig.11.3 Serial Control S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
VDIS VDIS External S1D15722 <Master> S1D15722 <Slave> power circuit Fig 13.1 Connection between Master and Slave Set V of master = HIGH, V of slave = Low, to supply V generated by master to slave. EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
(B) The display is enlarged lengthwise 224 × 368 dots by locating up and down (The SEG wiring must be divided in the midsection of the display. S1D15722 / Master synchronize Fig.14.2 Example of 2-chip Drive S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...
2. This development specification does not permit and guarantee the implementation and/or use of the patent properties and other intellectual property rights the third party or SEIKO EPSON owns. The applications provided in this development specification are for understanding of our products, and we are not responsible for any circuit problems that may occur when using them.
P4 and the description. P42 to 43 Added P4=0: n-line frame inversion overlap OFF P4=1: n-line frame inversion overlap ON In 7.2 Command table, at (26) Select MLS Drive command, add Added a bit P4. S1D15722D01B000 Technical Manual (Rev.1.1) EPSON...