8-Bit Dual Monochrome Passive Lcd Panel Timing; Figure 7-36: 8-Bit Dual Monochrome Passive Lcd Panel Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

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7.5.7 8-Bit Dual Monochrome Passive LCD Panel Timing

FPFRAME
FPLINE
MOD
UD[3:0], LD[3:0]
FPLINE
MOD
FPSHIFT
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
S1D13505
X23A-A-001-14
LINE 1/241 LINE 2/242 LINE 3/243
1-1 1-5
1-2 1-6
1-3
1-7
1-4 1-8
241-1 241-5
241-2 241-6
241-3 241-7
241-4 241-8

Figure 7-36: 8-Bit Dual Monochrome Passive LCD Panel Timing

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
VDP
LINE 4/244 LINE 239/479 LINE 240/480
HDP
Epson Research and Development

Vancouver Design Center

VNDP
LINE 1/241 LINE 2/242
HNDP
1-637
1-638
1-639
1-640
241-637
241-638
241-639
241-640
Hardware Functional Specification
Issue Date: 01/02/02