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4 V
4121 to S1D13505 Interface
R
4.1 Hardware Description
NEC V
4121
R
WR#
SHB#
RD#
LCDCS#
LCDRDY
ADD[25:0]
DAT[15:0]
BUSCLK
V
DD
V
DD
Note:
When connecting the S1D13505 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
S1D13505
X23A-G-011-04
The NEC V
4121 microprocessor is specifically designed to support an external LCD
R
controller. It provides all the necessary internal address decoding and control signals
required by the S1D13505.
The diagram below shows a typical implementation utilizing the S1D13505.
ADD21
+3.3V
3
+2.5V
2
Figure 4-1: NEC V
4121 to S1D13505 Configuration Schematic
R
Note
For pin mapping see Table 3-1:, "Host Bus Interface Pin Mapping," on page 10.
Pull-up
System RESET
Epson Research and Development
Vancouver Design Center
S1D13505
WE0#
WE1#
RD#
CS#
WAIT#
RESET#
M/R#
AB[20:0]
DB[15:0]
BUSCLK
V
(+3.3V)
DD
BS#
RD/WR#
V
DD
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/05
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