S1D13505 Host Bus Interface; Pc Card Host Bus Interface Pin Mapping - Epson S1D13505 Technical Manual

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3 S1D13505 Host Bus Interface

Note

3.1 PC Card Host Bus Interface Pin Mapping

Note
Interfacing to the PC Card Bus
Issue Date: 01/02/05
The S1D13505 implements a 16-bit PC Card (PCMCIA) host bus interface which is used
to interface to the PC Card bus.
The PC Card host bus interface is selected by the S1D13505 on the rising edge of RESET#.
After releasing reset the bus interface signals assume their selected configuration. For
details on S1D13505 configuration, see Section 4.2, "S1D13505 Hardware Configuration"
on page 15.
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
The following table shows the functions of each host bus interface signal.
Table 3-1: PC Card Host Bus Interface Pin Mapping
S1D13505 Pin Name
AB[20:0]
DB[15:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
1
The bus signal A0 is not used by the S1D13505 internally.
2
Although a clock is not directly supplied by the PC Card interface, one is required by
the S1D13505 PC Card host bus interface. For an example of how this can be accom-
plished see the discussion on BUSCLK in Section 3.2, "PC Card Host Bus Interface
Signals" on page 12.
PC Card (PCMCIA)
1
A[20:0]
D[15:0]
-CE2
External Decode
External Decode
2
n/a
V
DD
-CE1
-OE
-WE
-WAIT
Inverted RESET
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S1D13505
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