Epson S1D13505 Technical Manual page 412

Page 14
Pin # FPGA Signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
S5U13505-D9000
X23A-G-002-04
Table 3-1: Connectors Pinout for Channel A7 (Continued)
S1D13505 Signal
chA7p11 N/C
chA7p12 N/C
chA7p13 A20
chA7p14 A18
chA7p15 A17
chA7p16 A16
chA7p17 N/C
chA7p18 A14
chA7p19 A13
chA7p20 A12
chA7p21 A11
chA7p22 A9
chA7p23 A8
chA7p24 A7
chA7p25 A6
chA7p26 A5
chA7p27 A3
chA7p28 A2
chA7p29 A1
chA7p30 A0
Channel A7
Pin #
SmZ
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Epson Research and Development
Vancouver Design Center
FPGA Signal S1D13505 Signal
GND GND
GND GND
chA7p34 A19
GND GND
GND GND
GND GND
chA7p33 A15
GND GND
GND GND
GND GND
chA7p32 A10
GND GND
GND GND
GND GND
GND GND
chA7p31 A4
GND GND
GND GND
GND GND
GND GND
Evaluation Board User Manual
Issue Date: 01/02/05