Fpm-Dram Self-Refresh Timing; Table 7-20: Fpm-Dram Cbr Self-Refresh Timing; Figure 7-21: Fpm-Dram Self-Refresh Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Epson Research and Development

Vancouver Design Center

7.3.6 FPM-DRAM Self-Refresh Timing

Memory
Clock
RAS#
CAS#
Symbol
t1
Internal memory clock
RAS# precharge time (REG[22h] bits 3-2 = 00)
t2
RAS# precharge time (REG[22h] bits 3-2 = 01 or 10)
RAS# to CAS# precharge time (REG[22h] bits 3-2 = 00)
t3
RAS# to CAS# precharge time (REG[22h] bits 3-2 = 01 or 10)
t4
CAS# setup time (CAS# before RAS# refresh)
Hardware Functional Specification
Issue Date: 01/02/02
Stopped for
suspend mode
t1
t2
t3 t4

Figure 7-21: FPM-DRAM Self-Refresh Timing

Table 7-20: FPM-DRAM CBR Self-Refresh Timing

Parameter
Restarted for
active mode
Min
40
2.45 t1 - 1
1.45 t1 - 1
2 t1
1 t1
0.45 t1 - 2
Page 73
Max Units
ns
ns
ns
ns
ns
ns
S1D13505
X23A-A-001-14