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Page 114
Performance Enhancement Register 0
REG[22h]
RC Timing
Reserved
Value Bit 1
bit 7
bits 6-5
REG[22h] bits [6:5]
S1D13505
X23A-A-001-14
RAS#-to-
RC Timing
CAS# Delay
Value Bit 0
Value
Note
Changing this register to non-zero value, or to a different non-zero value, should be done only
when there are no read/write DRAM cycles. This condition occurs when all of the following are
true: the Display FIFO is disabled (REG[23h] bit 7 = 1), and the Half Frame Buffer is disabled
(REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive (Reg[27h] bits 7-6 = 00). This condition also
occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset.
For further programming information, see S1D13505 Programming Notes and Examples, docu-
ment number X23A-G-003-xx.
Reserved
RC Timing Value (N
) Bits [1:0]
RC
These bits select the DRAM random-cycle timing parameter, t
(N
) of MCLK periods (T
RC
t
, the RAS pulse width. Use the following two formulae to calculate N
RAS
value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
N
= Round-Up (t
RC
N
= Round-Up (t
RC
= Round-Up (t
The resulting t
is related to N
RC
t
= (N
) T
RC
RC
Table 8-12: Minimum Memory Timing Selection
00
01
10
11
RAS#
RAS#
Precharge
Precharge
Timing Value
Timing Value
Bit 1
Bit 0
) used to create t
. N
M
RC
RC
/T
)
RC
M
/T
+ N
)
if N
RAS
M
RP
/T
+ 1.55)
if N
RAS
M
as follows:
RC
M
N
RC
5
4
3
Reserved
Epson Research and Development
Vancouver Design Center
Reserved
. These bits specify the number
RC
should be chosen to meet t
RC
then choose the larger
RC
= 1 or 2
RP
= 1.5
RP
Minimum Random Cycle
t
Width (
)
RC
5
4
3
Reserved
Hardware Functional Specification
Issue Date: 01/02/02
RW
Reserved
as well as
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