Epson S1D13505 Technical Manual page 414

Page 16
Pin # FPGA Signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
S5U13505-D9000
X23A-G-002-04
Table 3-2: Connectors Pinout for Channel A6 (Continued)
S1D13505 Signal
chA6p11 M/R#
chA6p12 RD#
chA6p13 WE1#
chA6p14 RESET#
chA6p15 N/C
chA6p16 N/C
chA6p17 N/C
chA6p18 D14
chA6p19 D13
chA6p20 D12
chA6p21 D11
chA6p22 D9
chA6p23 D8
chA6p24 D7
chA6p25 D6
chA6p26 D5
chA6p27 D3
chA6p28 D2
chA6p29 D1
chA6p30 D0
Channel A6
Pin #
SmZ
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Epson Research and Development
Vancouver Design Center
FPGA Signal S1D13505 Signal
GND GND
GND GND
chA6p34 N/C
GND GND
GND GND
GND GND
chA6p33 D15
GND GND
GND GND
GND GND
chA6p32 D10
GND GND
GND GND
GND GND
GND GND
chA6p31 D4
GND GND
GND GND
GND GND
GND GND
Evaluation Board User Manual
Issue Date: 01/02/05