Pc Card Interface Timing; Figure 7-5: Pc Card Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Embedded ramdac lcd/crt controller
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7.1.5 PC Card Interface Timing

CLK
A[20:0]
M/R#
-CE[1:0]
CS#
-OE
-WE
-WAIT
D[15:0](write)
D[15:0](read)
S1D13505
X23A-A-001-14
t1
t2
t3
t4
t7
t11

Figure 7-5: PC Card Timing

Note
The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is
selected.
t9
Epson Research and Development

Vancouver Design Center

t5
t6
t8
t10
t13
t12
Hardware Functional Specification
Issue Date: 01/02/02

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