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Epson Research and Development
Vancouver Design Center
Symbol
t1
Clock period
t2
Clock pulse width low
t3
Clock pulse width high
t4
ADDR[12:0] setup to first CLK of cycle
t5
ADDR[12:0] hold from command invalid
t6
ADDR[12:0] setup to falling edge ALE
t7
ADDR[12:0] hold from falling edge ALE
t8
CARDREG* hold from command invalid
1
t9
Falling edge of chip select to CARDxWAIT* driven
t10
Command invalid to CARDxWAIT* tri-state
t11
D[31:16] valid to first CLK of cycle (write cycle)
t12
D[31:16] hold from rising edge of CARDxWAIT*
2
t13
Chip select to D[31:16] driven (read cycle)
t14
D[31:16] setup to rising edge CARDxWAIT* (read cycle)
t15
Command invalid to D[31:16] tri-state (read cycle)
Note
90%
V
IH
V IL
10%
t r
Symbol
T
OSC
t
PWH
t
PWL
t
f
t
r
Hardware Functional Specification
Issue Date: 01/02/02
Table 7-10: Toshiba Timing
Parameter
1.
If the S1D13505 host interface is disabled, the timing for CARDxWAIT* driven is relative to
the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0]
becomes valid, whichever one is later.
2.
If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the
falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] be-
comes valid, whichever one is later.
The Toshiba interface has different clock input requirements as follows:
t
PWH
Figure 7-11: Clock Input Requirement
Table 7-11: Clock Input Requirements for BUSCLK using Toshiba local bus
Parameter
Input Clock Period)
Input Clock Pulse Width High
Input Clock Pulse Width Low
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
Min
13.3
5.4
5.4
10
0
10
5
0
0
5
10
0
1
0
5
t
PWL
t
f
T
OSC
Min
13.3
5.4
5.4
3.0V
5.0V
Max
Min
Max
13.3
5.4
5.4
10
0
10
5
0
15
0
9
25
2.5
10
10
0
1
0
25
2.5
10
Max
Units
ns
ns
ns
5
ns
5
ns
X23A-A-001-14
Page 59
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S1D13505
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