Mc68K Bus 2 Interface Timing (E.g. Mc68030); Figure 7-4: Mc68030 Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Page 48

7.1.4 MC68K Bus 2 Interface Timing (e.g. MC68030)

CLK
A[20:0]
SIZ[1:0] M/R#
CS#
AS#
DS#
R/W#
DSACK1#
D[31:16](write)
D[31:16](read)
S1D13505
X23A-A-001-14
t1 t2 t3
t4
t7
t9
t14

Figure 7-4: MC68030 Timing

Note
The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is
selected.
t12
t15
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Vancouver Design Center

t5
t6
t17
t11
t8
t10
t13
t16
Hardware Functional Specification
Issue Date: 01/02/02