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7.1.10 Power PC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)
CLKOUT
A[11:31], RD/WR#
TSIZ[0:1], M/R#
CS#
TS#
TA#
BI#
D[0:15](write)
D[0:15](read)
S1D13505
X23A-A-001-14
t1
t2
t3
t4
t6
t8
t9
t10
t14
Figure 7-12: Power PC Timing
Note
The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is
selected.
t17
t19
Epson Research and Development
Vancouver Design Center
t5
t7
t11
t12
t13
t15 t16
t18
t20
t21
Hardware Functional Specification
Issue Date: 01/02/02