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Epson Research and Development
Vancouver Design Center
8 Registers
8.1 Register Mapping
CS#
0
0
1
8.2 Register Descriptions
8.2.1 Revision Code Register
Revision Code Register
REG[00h]
Product Code
Product Code
Bit 5
Bit 4
bits 7-2
bits 1-0
Hardware Functional Specification
Issue Date: 01/02/02
The S1D13505 registers are memory mapped. The system addresses the registers through the CS#,
M/R#, and AB[5:0] input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address
bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] =
000001. See the table below:
Table 8-1: S1D13505 Addressing
M/R#
Register access:
• REG[00h] is addressed when AB[5:0] = 0
0
• REG[01h] is addressed when AB[5:0] = 1
• REG[n] is addressed when AB[5:0] = n
Memory access: the 2M byte Display Buffer is addressed by
1
AB[20:0]
X
S1D13505 not selected
Unless specified otherwise, all register bits are reset to 0 during power-on. Reserved bits should be
written 0 when programming unless otherwise noted.
Product Code
Product Code
Bit 3
Bit 2
Product Code Bits [5:0]
This is a read-only register that indicates the product code of the chip. The product code for the
S1D13505 is 000011.
Revision Code Bits [1:0]
This is a read-only register that indicates the revision code of the chip. The revision code for the
S1D13505F00A is 00.
Access
Product Code
Product Code
Bit 1
Bit 0
Page 99
RO
Revision
Revision
Code Bit 1
Code Bit 0
S1D13505
X23A-A-001-14
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