Mpc821 To S1D13505 Interface; Hardware Description - Epson S1D13505 Technical Manual

Epson Research and Development
Vancouver Design Center

4 MPC821 to S1D13505 Interface

4.1 Hardware Description

Note:
When connecting the S1D13505 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of MPC821 to S1D13505 Interface
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/05
The S1D13505 provides native Power PC bus support making it very simple to interface
the two devices. This application note describes both the environment necessary to connect
the S1D13505 to the MPC821 native system bus and the connection between the
S5U13505B00B Evaluation Board and the Motorola MPC821 Application Development
System (ADS).
Additionally, by implementing a dedicated display buffer, the S1D13505 can reduce
system power consumption, improve image quality, and increase system performance as
compared to the MPC821's on-chip LCD controller.
The S1D13505, through the use of the MPC821 chip selects, can share the system bus with
all other MPC821 peripherals. The following figure demonstrates a typical implementation
of the S1D13505 to MPC821 interface.
MPC821
A10
A[11:31]
D[0:15]
CS4
TS
TA
RD/WR
TSIZ0
TSIZ1
BI
SYSCLK
System
RESET
S1D13505
M/R#
AB[20:0]
DB[15:0]
CS#
BS#
WAIT#
RD/WR#
RD#
WE0#
WE1#
BUSCLK
RESET#
Page 15
S1D13505
X23A-G-008-05