Table 7-7: Mips/Isa Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Epson Research and Development

Vancouver Design Center

Symbol
t1
Clock period
t2
Clock pulse width high
t3
Clock pulse width low
LatchA20, SA[19:0], M/R#, SBHE# setup to first BUSCLK where
t4
CS# = 0 and either MEMR# = 0 or MEMW# = 0
LatchA20, SA[19:0], M/R#, SBHE# hold from rising edge of
t5
either MEMR# or MEMW#
t6
CS# hold from rising edge of either MEMR# or MEMW#
Falling edge of either MEMR# or MEMW# to IOCHRDY# driven
1
t7
low
t8
Rising edge of either MEMR# or MEMW# to IOCHRDY# tri-state
SD[15:0] setup to third BUSCLK where CS# = 0 MEMW# = 0
t9
(write cycle)
t10
SD[15:0] hold (write cycle)
2
t11
Falling edge MEMR# to SD[15:0] driven (read cycle)
t12
SD[15:0] setup to rising edge IOCHRDY# (read cycle)
t13
Rising edge of MEMR# toSD[15:0] tri-state (read cycle)
Hardware Functional Specification
Issue Date: 01/02/02

Table 7-7: MIPS/ISA Timing

Parameter
1. If the S1D13505 host interface is disabled, the timing for IOCHRDY driven low is relative to
the falling edge of MEMR#, MEMW# or the first positive edge of BUSCLK after LatchA20,
SA[19:0], M/R# becomes valid, whichever one is later.
2. If the S1D13505 host interface is disabled, the timing for SD[15:0] driven is relative to the
falling edge of MEMR# or the first positive edge of BUSCLK after LatchA20, SA[19:0],
M/R# becomes valid, whichever one is later.
3.0V 5.0V
Min Max Min
20 20
6 6
6 6
10 10
0 0
0 0
0 0
5 25 2.5
10 10
0 0
0 0
0 0
5 25 5
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Max Units
ns
ns
ns
ns
ns
ns
ns
10 ns
ns
ns
ns
ns
10 ns
S1D13505
X23A-A-001-14