Vancouver Design Center - Epson S1D13505 Technical Manual

Page 108
Screen 1 Display Start Address Register 0
REG[10h]
Start Address Start Address
Bit 7 Bit 6
Screen 1 Display Start Address Register 1
REG[11h]
Start Address Start Address
Bit 15 Bit 14
Screen 1 Display Start Address Register 2
REG[12h]
n/a n/a
REG[10h] bits 7-0
REG[11h] bits 7-0
REG[12h] bits 3-0
Screen 2 Display Start Address Register 0
REG[13h]
Start Address Start Address
Bit 7 Bit 6
Screen 2 Display Start Address Register 1
REG[14h]
Start Address Start Address
Bit 15 Bit 14
Screen 2 Display Start Address Register 2
REG[15h]
n/a n/a
REG[13h] bits 7-0
REG[14h] bits 7-0
REG[15h] bits 3-0
S1D13505
X23A-A-001-14
Start Address Start Address
Bit 5 Bit 4
Start Address Start Address
Bit 13 Bit 12
n/a n/a
Screen 1 Start Address Bits [19:0]
These registers form the 20-bit address for the starting word of the Screen 1 image in
the display buffer.
Note that this is a word address.
A combination of this register and the Pixel Panning register (REG[18h]) can be used to uniquely
identify the start (top left) pixel within the Screen 1 image stored in the display buffer.
See "Display Configuration" for details.
Start Address Start Address
Bit 5 Bit 4
Start Address Start Address
Bit 13 Bit 12
n/a n/a
Screen 2 Start Address Bits [19:0]
These registers form the 20-bit address for the starting word of the Screen 2 image in
the display buffer.
Note that this is a word address.
A combination of this register and the Pixel Panning register (REG[18h]) can be used to uniquely
identify the start (top left) pixel within the Screen 2 image stored in the display buffer.
See "Display Configuration" for details.
Start Address Start Address
Bit 3 Bit 2
Start Address Start Address
Bit 11 Bit 10
Start Address Start Address
Bit 19 Bit 18
Start Address Start Address
Bit 3 Bit 2
Start Address Start Address
Bit 11 Bit 10
Start Address Start Address
Bit 19 Bit 18
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Start Address Start Address
Bit 1 Bit 0
Start Address Start Address
Bit 9 Bit 8
Start Address Start Address
Bit 17 Bit 16
Start Address Start Address
Bit 1 Bit 0
Start Address Start Address
Bit 9 Bit 8
Start Address Start Address
Bit 17 Bit 16
Hardware Functional Specification
Issue Date: 01/02/02
RW
RW
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RW