Access Cycles - Epson S1D13505 Technical Manual

Epson Research and Development
Vancouver Design Center

2.1.2 Access Cycles

SDCLKOUT
A[23:1]
LLBEN,
LUBEN
CSn
IORD,
IOWR
D[15:0]
(write)
D[15:0]
(read)
READY
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/05
Once an address in the appropriate range is placed on the external address bus (A[23:1]),
the corresponding chip select (CSn) is driven low. The read or write enable signals (IORD
or IOWR) are driven low and READY is driven low by the S1D13505 to insert wait states
into the cycle. The byte enable signals (LLBEN and LUBEN) allow byte steering.
The following figure illustrates typical NEC V832 memory-mapped IO access cycles.
Hi-Z
Figure 2-1: NEC V832 Read/Write Cycles
VALID
VALID
VALID
S1D13505
X23A-G-012-02
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