Table 7-24: 8-Bit Single Monochrome Passive Lcd Panel A.c. Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Epson Research and Development

Vancouver Design Center

Sync Timing
Data Timing
Symbol
t1
FPFRAME setup to FPLINE pulse trailing edge
t2
FPFRAME hold from FPLINE pulse trailing edge
t3
FPLINE pulse width
t4
FPLINE period
t5
MOD transition to FPLINE pulse trailing edge
t6
FPSHIFT falling edge to FPLINE pulse leading edge
t7 FPLINE pulse trailing edge to FPSHIFT falling edge
t8
FPSHIFT period
t9 FPSHIFT falling edge to FPLINE pulse trailing edge
t10
FPLINE pulse trailing edge to FPSHIFT rising edge
t11
FPSHIFT pulse width high
t12
FPSHIFT pulse width low
t13
UD[3:0], LD[3:0] setup to FPSHIFT falling edge
t14
UD[3:0], LD[3:0] hold to FPSHIFT falling edge
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1 = t4 - 14Ts
min min
3. t4 = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
min
4. t5 = [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts
min
5. t6 = [((REG[05h] bits [4:0]) + 1)*8 - 25] Ts
min
6. t9 = [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts
min
Hardware Functional Specification
Issue Date: 01/02/02
FPFRAME
FPLINE
MOD
FPLINE
FPSHIFT
UD[3:0]
LD[3:0]
Figure 7-27: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing

Table 7-24: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing

Parameter
t1
t2
t3
t5
t6
t7
t10
t9
t13
Min
note 2
14
9
note 3
1
note 5
t10 + t11
8
note 6
20
4
4
4
4
t4
t8
t11 t12
t14
1 2
Typ Max
Ts (note 1)
note 4
X23A-A-001-14
Page 79
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
S1D13505