Interfacing To The Nec V832; The Nec V832 System Bus; Overview - Epson S1D13505 Technical Manual

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2 Interfacing to the NEC V832

2.1 The NEC V832 System Bus

2.1.1 Overview

S1D13505
X23A-G-012-02
This section provides an overview of the operation of the CPU bus in order to establish
interface requirements.
The NEC V832 is designed around the RISC architecture developed by MIPS. This
microprocessor is based on the 32-bit V830 CPU core. The CPU communicates with
external devices via the Bus Control Unit (BCU). The BCU in turn communicates using its
ADD and DATA buses which can be dynamically sized to 16 or 32-bit operation.
The NEC V832 features dedicated chip select pins which allow memory-mapped IO
operations. A 16M byte block of addressing space can be assigned for the LCD controller
and its own chip select and ready signals are available. Word or byte accesses are controlled
by system byte enable signals (LLBEN and LUBEN).
Epson Research and Development
Vancouver Design Center
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/05