16-Bit Tft/D-Tfd Panel Timing; Figure 7-42: 16-Bit Tft/D-Tfd Panel Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

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7.5.10 16-Bit TFT/D-TFD Panel Timing

FPFRAME
FPLINE
R[5:1], G[5:0], B[5:1]
DRDY
FPLINE
FPSHIFT
DRDY
R[5:1]
G [5:0]
B[5:1]
Note: DRDY is used to indicate the first pixel
Example Timing for 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
S1D13505
X23A-A-001-14
VNDP
LINE480
HNDP
1

Figure 7-42: 16-Bit TFT/D-TFD Panel Timing

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= HNDP
VDP
LINE1
HDP
1-1 1-2
1-1
1-2
1-1 1-2
+ HNDP = ((REG[05h] bits [4:0]) + 1)*8Ts
1 2
Epson Research and Development

Vancouver Design Center

LINE480
HNDP
2
1-640
1-640
1-640
Hardware Functional Specification
Issue Date: 01/02/02