S1D13505 Hardware Configuration; Performance - Epson S1D13505 Technical Manual

Embedded ramdac lcd/crt controller
Table of Contents

Advertisement

Epson Research and Development
Vancouver Design Center

4.2 S1D13505 Hardware Configuration

S1D13505
Pin Name
MD0
8-bit host bus interface
MD[3:1]
111 = PC Card host bus interface selected
MD4
Little Endian
MD5
WAIT# is active high (1 = insert wait state)
MD11
Alternate Host Bus Interface Selected
MD12
BUSCLK input divided by two
= configuration for PC Card host bus interface

4.3 Performance

Interfacing to the PC Card Bus
Issue Date: 01/02/05
The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
The table below shows only those configuration settings important to the PC Card host bus
interface.
Table 4-1: Summary of Power-On/Reset Options
value on this pin at rising edge of RESET# is used to configure:(1/0)
1
The S1D13505 PC Card Interface specification supports a BCLK up to 50MHz, and
therefore can provide a high performance display solution.
0
16-bit host bus interface
Big Endian
WAIT# is active low (0 = insert wait state)
Primary Host Bus Interface Selected
BUSCLK input not divided by two
Page 15
S1D13505
X23A-G-005-06

Advertisement

Table of Contents
loading

Table of Contents