Serial Interface; Configuration Of Serial Interface - Epson 0C88832 Technical Manual

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

5.7 Serial Interface

5.7.1 Configuration of serial interface

The E0C88832/88862 incorporates a full duplex
serial interface (when asynchronous system is
selected) that allows the user to select either clock
synchronous system or asynchronous system.
The data transfer method can be selected in soft-
ware.
When the clock synchronous system is selected, 8-
bit data transfer is possible.
When the asynchronous system is selected, either 7-
bit or 8-bit data transfer is possible, and a parity
check of received data and the addition of a parity
bit for transmitting data can automatically be done
by selecting in software.
Figure 5.7.1.1 shows the configuration of the serial
interface.
Serial interface input/output terminals, SIN, SOUT,
SCLK and SRDY are shared with I/O ports P10–P13.
In order to utilize these terminals for the serial
interface input/output terminals, proper settings
have to be made with registers ESIF, SMD0 and
SMD1. (At initial reset, these terminals are set as I/O
port terminals.)
The direction of I/O port terminals set for serial
interface input/output terminals are determined by
the signal and transfer mode for each terminal.
Furthermore, the settings for the corresponding I/O
control registers for the I/O ports become invalid.
Serial I/O control
& status register
Serial input
SIN(P10)
control circuit
Start bit
detection circuit
SCLK(P12)
48
SIN and SOUT are serial data input and output
terminals which function identically in clock
synchronous system and asynchronous system.
SCLK is exclusively for use with clock synchronous
system and functions as a synchronous clock input/
output terminal. SRDY is exclusively for use in clock
synchronous slave mode and functions as a send-
receive ready signal output terminal.
When asynchronous system is selected, since SCLK
and SRDY are superfluous, the I/O port terminals
P12 and P13 can be used as I/O ports.
In the same way, when clock synchronous master
mode is selected, since SRDY is superfluous, the I/O
port terminal P13 can be used as I/O port.
Data bus
Received Error detection
data buffer circuit
Received data
shift register
Clock
f
control circuit
OSC3
Fig. 5.7.1.1 Configuration of serial interface
EPSON
Table 5.7.1.1 Configuration of input/output terminals
Terminal When serial interface is selected
P10
P11
P12
P13
* The terminals used may vary depending on the transfer mode.
Interrupt
control circuit
Transmitting data Serial output
shift register control circuit
READY output
control circuit
OSC3 oscillation circuit
Programmable timer 1 underflow signal
E0C88832/88862 TECHNICAL MANUAL
SIN
SOUT
SCLK
SRDY
Interrupt
request
SOUT(P11)
SRDY(P13)