Figure 3-7: Typical System Diagram (Philips Pr31500/Pr31700 Bus); Figure 3-8: Typical System Diagram (Toshiba Tx3912 Bus) - Epson S1D13505 Technical Manual

Page 18
Philips
PR31500
/PR31700
BUS
A[12:0]
D[31:16]
ALE
/CARDREG
/CARDIORD
/CARDIOWR
/CARDxCSH
/CARDxCSL
/RD
/WE
/CARDxWAIT
DCLKOUT
RESET#
Toshiba
TX3912 BUS
A[12:0]
D[23:16]
D[31:24]
ALE
CARDREG*
CARDIORD*
CARDIOWR*
CARDxCSH*
CARDxCSL*
RD*
WE*
CARDxWAIT*
DCLKOUT
RESET#
S1D13505
X23A-A-001-14
Power
Management
M/R#
CS#
BS#
AB[16:13]
AB[12:0]
DB[15:0]
AB20
AB19
AB18
AB17
WE1#
RD/WR#
RD#
WE0#
WAIT#
BUSCLK
RESET#

Figure 3-7: Typical System Diagram (Philips PR31500/PR31700 Bus)

Power
Management
M/R#
CS#
BS#
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
AB20
AB19
AB18
AB17
WE1#
RD/WR#
RD#
WE0#
WAIT#
BUSCLK
RESET#

Figure 3-8: Typical System Diagram (Toshiba TX3912 Bus)

.
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
S1D13505F00A
LCDPWR
RED,GREEN,BLUE
1Mx16
FPM/EDO-DRAM
.
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
S1D13505F00A
LCDPWR
RED,GREEN,BLUE
1Mx16
FPM/EDO-DRAM
Epson Research and Development
Vancouver Design Center
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
Display
FPFRAME
FPLINE
DRDY
MOD
CRT
HRTC
Display
VRTC
IREF
IREF
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
FPFRAME Display
FPLINE
DRDY
MOD
CRT
HRTC
Display
VRTC
IREF
IREF
Hardware Functional Specification
Issue Date: 01/02/02