Table of Contents
Advertisement
Epson Research and Development
Vancouver Design Center
50,
84,
30,
50,
16
};
/*===========================================================================
**
HAL_REGS.H
**
Created 1998, Epson Research & Development
**
**
Copyright(c) Epson Research and Development Inc. 1997, 1998.
=============================================================================*/
#ifndef __HAL_REGS_H__
#define __HAL_REGS_H__
/*
** 1355 register names
*/
#define REG_REVISION_CODE
#define REG_MEMORY_CONFIG
#define REG_PANEL_TYPE
#define REG_MOD_RATE
#define REG_HORZ_DISP_WIDTH
#define REG_HORZ_NONDISP_PERIOD
#define REG_HRTC_START_POSITION
#define REG_HRTC_PULSE_WIDTH
#define REG_VERT_DISP_HEIGHT0
#define REG_VERT_DISP_HEIGHT1
#define REG_VERT_NONDISP_PERIOD
#define REG_VRTC_START_POSITION
#define REG_VRTC_PULSE_WIDTH
#define REG_DISPLAY_MODE
#define REG_SCRN1_LINE_COMPARE0
#define REG_SCRN1_LINE_COMPARE1
#define REG_SCRN1_DISP_START_ADDR0
#define REG_SCRN1_DISP_START_ADDR1
#define REG_SCRN1_DISP_START_ADDR2
#define REG_SCRN2_DISP_START_ADDR0
#define REG_SCRN2_DISP_START_ADDR1
#define REG_SCRN2_DISP_START_ADDR2
#define REG_MEM_ADDR_OFFSET0
#define REG_MEM_ADDR_OFFSET1
#define REG_PIXEL_PANNING
Programming Notes and Examples
Issue Date: 01/02/05
/* Memory speed in ns */
/* Ras to Cas Delay in ns */
/* Ras Access Charge time in ns */
/* RAS Access Charge time in ns */
/* Host CPU bus width in bits */
The following header file defines the S1D13505 HAL registers.
Vancouver Design Center.
reserved.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
Page 97
All rights
S1D13505
X23A-G-003-07
Advertisement
Chapters
Table of Contents
