Table 7-26: 8-Bit Single Color Passive Lcd Panel A.c. Timing (Format 1); Figure 7-31: 8-Bit Single Color Passive Lcd Panel A.c. Timing (Format 1); Vancouver Design Center - Epson S1D13505 Technical Manual

Epson Research and Development

Vancouver Design Center

Sync Timing
Data Timing
Symbol
t1
FPFRAME setup to FPLINE pulse trailing edge
t2
FPFRAME hold from FPLINE pulse trailing edge
t3
FPLINE pulse width
t4
FPLINE period
t5a
FPSHIFT2 falling edge to FPLINE pulse leading edge
t5b
FPSHIFT falling edge to FPLINE pulse leading edge
FPLINE pulse trailing edge to FPSHIFT2 rising, FPSHIFT falling
t6
edge
t7
FPSHIFT2, FPSHIFT period
t8a
FPSHIFT falling edge to FPLINE pulse trailing edge
t8b
FPSHIFT2 falling edge to FPLINE pulse trailing edge
t9
FPLINE pulse trailing edge to FPSHIFT rising edge
t10
FPSHIFT2, FPSHIFT pulse width high
t11
FPSHIFT2, FPSHIFT pulse width low
t12
UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge
t13
UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1 = t4 - 14Ts
min min
3. t4 = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
min
4. t5 = [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts
min
5. t5 = [((REG[05h] bits [4:0]) + 1)*8 - 29] Ts
min
6. t8 = [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts
min
7. t8 = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts
min
Hardware Functional Specification
Issue Date: 01/02/02
FPFRAME
FPLINE
FPLINE
t5a
FPSHIFT
FPSHIFT2
UD[3:0]
LD[3:0]

Figure 7-31: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)

Table 7-26: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)

Parameter
t1
t2
t3
t5b
t6
t8a t9
t8b
t12
note 2
note 3
note 4
note 5
t9 + t10
note 6
note 7
t4
t7
t10 t11
t13
1 2
Min Typ Max
14
9
4
20
2
2
1
1
Page 83
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
S1D13505
X23A-A-001-14