Table 8-8: Pixel Panning Selection; Vancouver Design Center - Epson S1D13505 Technical Manual

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Vancouver Design Center

Memory Address Offset Register 0
REG[16h]
Memory Memory
Address Address
Offset Bit 7 Offset Bit 6
Memory Address Offset Register 1
REG[17h]
n/a n/a
REG[16h] bits 7-0
REG[17h] bits 2-0
Pixel Panning Register
REG[18h]
Screen 2 Screen 2
Pixel Panning Pixel Panning
Bit 3 Bit 2
Display Mode
15/16 bpp
bits 7-4
bits 3-0
Hardware Functional Specification
Issue Date: 01/02/02
Memory Memory
Address Address
Offset Bit 5 Offset Bit 4
n/a n/a
Memory Address Offset Bits [10:0]
These bits form the 11-bit address offset from the starting word of line n to the starting word of line
n+1. This value is applied to both Screen 1 and Screen 2.
Note that this value is in words.
A virtual image can be formed by setting this register to a value greater than the width of the dis-
play. The displayed image is a window into the larger virtual image.
See "Section 10 Display Configuration" for details.
Screen 2 Screen 2
Pixel Panning Pixel Panning
Bit 1 Bit 0
This register is used to control the horizontal pixel panning of Screen 1 and Screen 2. Each screen
can be independently panned to the left by programming its respective Pixel Panning Bits to a non-
zero value. The value represents the number of pixels panned. The maximum pan value is dependent
on the display mode.

Table 8-8: Pixel Panning Selection

Maximum Pan Value
1 bpp
2 bpp
4 bpp
8 bpp
Smooth horizontal panning can be achieved by a combination of this register and the Display Start
Address registers.
See "Section 10 Display Configuration" for details.
Screen 2 Pixel Panning Bits [3:0]
Pixel panning bits for screen 2.
Screen 1 Pixel Panning Bits [3:0]
Pixel panning bits for screen 1.
Memory Memory
Address Address
Offset Bit 3 Offset Bit 2
Memory
n/a Address
Offset Bit 10
Screen 1 Screen 1
Pixel Panning Pixel Panning
Bit 3 Bit 2
Pixel Panning Bits active
16
8
4
1
0
Memory Memory
Address Address
Offset Bit 1 Offset Bit 0
Memory Memory
Address Address
Offset Bit 9 Offset Bit 8
Screen 1 Screen 1
Pixel Panning Pixel Panning
Bit 1 Bit 0
Bits [3:0]
Bits [2:0]
Bits [1:0]
Bit 0
none
S1D13505
X23A-A-001-14
Page 109
RW
RW
RW