D9000 Specifics; Interface Signals; Connector Pinout For Channel A6 And A7 - Epson S1D13505 Technical Manual

Epson Research and Development
Vancouver Design Center

3 D9000 Specifics

3.1 Interface Signals

3.1.1

Connector Pinout for Channel A6 and A7

Pin # FPGA Signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Evaluation Board User Manual
Issue Date: 01/02/05
The S5U13505-D9000 is designed to support the standard Register Interface of the Windows CE
development platform together with the FPGA code that comes with the board.
Table 3-1: Connectors Pinout for Channel A7
S1D13505 Signal
chA7p1 BCLK
chA7p2 N/C
chA7p3 N/C
chA7p4 N/C
chA7p5 N/C
chA7p6 N/C
chA7p7 N/C
chA7p8 N/C
chA7p9 N/C
chA7p10 N/C
ib8 N/C
ib7 N/C
ib6 N/C
ib5 N/C
ib4 N/C
ib3 N/C
ib2 N/C
ib1 N/C
GND GND
GND GND
Channel A7
Pin #
SmXY
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FPGA Signal S1D13505 Signal
dc5v DC5V
GND GND
dc3v DC3V
GND GND
dc3v DC3V
GND GND
dc3vs N/C
GND GND
dc12v DC12V
GND GND
battery N/C
GND GND
dcXA N/C
base5vDc N/C
dcXB N/C
GND GND
dcXC N/C
GND GND
senseH N/C
senseL N/C
S5U13505-D9000
X23A-G-002-04
Page 13