Epson S1D13505 Technical Manual page 247

Embedded ramdac lcd/crt controller
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Epson Research and Development
Vancouver Design Center
/*
** Registers 28-29: Cursor X Position
*/
*(pRegs + 0x28) = 0x00;
*(pRegs + 0x29) = 0x00;
/*
** Registers 2A-2B: Cursor Y Position
*/
*(pRegs + 0x2A) = 0x00;
*(pRegs + 0x2B) = 0x00;
/*
** Registers 2C-2D: Ink/Cursor Color 0 - blue
*/
*(pRegs + 0x2C) = 0x1F;
*(pRegs + 0x2D) = 0x00;
/*
** Registers 2E-2F: Ink/Cursor Color 1 - green
*/
*(pRegs + 0x2E) = 0xE0;
*(pRegs + 0x2F) = 0x07;
/*
** Register 30: Ink/Cursor Start Address Select
*/
*(pRegs + 0x30) = 0x00;
/*
** Register 31: Alternate FRM Register
*/
*(pRegs + 0x31) = 0x00;
/*
** Register 23: Performance Enhancement - display FIFO enabled, optimum
**
**
**
*/
*(pRegs + 0x23) = 0x00;
/*
** Register D: Display Mode - 8 BPP, LCD enable.
*/
*(pRegs + 0x0D) = 0x0D;
/*
** Clear memory by filling 2 MB with 0
*/
pMem = DISP_MEM_OFFSET;
for (lpCnt = 0; lpCnt < DISP_MEMORY_SIZE; lpCnt++)
{
*pMem = 0;
pMem++;
}
/*
Programming Notes and Examples
Issue Date: 01/02/05
performance. The FIFO threshold is set to 0x00; for
15/16 bpp modes, set the FIFO threshold
to a higher value, such as 0x1B.
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0001 1111 */
/* 0000 0000 */
/* 1110 0000 */
/* 0000 0111 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 1101 */
Page 93
S1D13505
X23A-G-003-07

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