Epson S1D13505 Technical Manual page 543

Epson Research and Development
Vancouver Design Center
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4-2: NEC V832 Wait States vs. Bus Clock Frequency . . . . . . . . . . . . . . . . . . . . . 14
Table 4-3: NEC V832 IO Address Range For Each CSn Line . . . . . . . . . . . . . . . . . . . . 15
Figure 2-1: NEC V832 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: NEC V832 to S1D13505 Configuration Schematic . . . . . . . . . . . . . . . . . . . . 12
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/05
List of Tables
List of Figures
Page 5
S1D13505
X23A-G-012-02