Table 7-27: 8-Bit Single Color Passive Lcd Panel A.c. Timing (Format 2); Figure 7-33: 8-Bit Single Color Passive Lcd Panel A.c. Timing (Format 2); Vancouver Design Center - Epson S1D13505 Technical Manual

Epson Research and Development

Vancouver Design Center

Sync Timing
Data Timing
Symbol
t1
FPFRAME setup to FPLINE pulse trailing edge
t2
FPFRAME hold from FPLINE pulse trailing edge
t3
FPLINE period
t4
FPLINE pulse width
t5
MOD transition to FPLINE pulse trailing edge
t6
FPSHIFT falling edge to FPLINE pulse leading edge
t7
FPSHIFT falling edge to FPLINE pulse trailing edge
t8
FPLINE pulse trailing edge to FPSHIFT falling edge
t9
FPSHIFT period
t10
FPSHIFT pulse width low
t11
FPSHIFT pulse width high
t12
UD[3:0], LD[3:0] setup to FPSHIFT falling edge
t13
UD[3:0], LD[3:0] hold to FPSHIFT falling edge
t14
FPLINE pulse trailing edge to FPSHIFT rising edge
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1 = t3 - 14Ts
min min
3. t3 = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
min
4. t5 = [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts
min
5. t6 = [((REG[05h] bits [4:0]) + 1)*8 - 28] Ts
min
6. t7 = [((REG[05h] bits [4:0]) + 1)*8 - 19] Ts
min
Hardware Functional Specification
Issue Date: 01/02/02
FPFRAME
FPLINE
MOD
FPLINE
FPSHIFT
UD[3:0]
LD[3:0]

Figure 7-33: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)

Table 7-27: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)

Parameter
t1
t2
t4
t5
t6
t8
t7 t14
t12
t3
t9
t11 t10
t13
1 2
Min Typ Max
note 2
14
note 3
9
1 note 4
note 5
note 6
t14 + 2
2
1
1
1
1
20
Page 85
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
S1D13505
X23A-A-001-14