Table 8-11: Ma/Gpio Pin Functionality; Vancouver Design Center - Epson S1D13505 Technical Manual

Page 112
MD Configuration Readback Register 0
REG[1Ch]
MD[7] Status MD[6] Status
MD Configuration Readback Register 1
REG[1Dh]
MD[15] MD[14]
Status Status
REG[1Ch] bits 7-0
REG[1Dh] bits 7-0
General IO Pins Configuration Register 0
REG[1Eh]
n/a n/a
MD[7:6] at
rising edge of
bit 3
bit 2
bit 1
S1D13505
X23A-A-001-14
MD[5] Status MD[4] Status
MD[13] MD[12]
Status Status
MD[15:0] Configuration Status
These are read-only status bits for the MD[15:0] pins configuration status at the rising edge of
RESET#. MD[15:0] are used to configure the chip at the rising edge of RESET# – see Pin Descrip-
tions and Summary of Configuration Options for details.
n/a n/a
Pins MA9, MA10, MA11 are multi-functional – they can be DRAM address outputs or general
purpose IO dependent on the DRAM type. MD[7:6] are used to identify the DRAM type and
configure these pins as follows:

Table 8-11: MA/GPIO Pin Functionality

MA9
RESET#
00 GPIO3
01 MA9
10 MA9
11 MA9
These bits are used to control the direction of these pins when they are used as general purpose IO.
These bits have no effect when the pins are used as DRAM address outputs.
GPIO3 Pin IO Configuration
When this bit = 1, the GPIO3 pin is configured as an output pin.
When this bit = 0 (default), the GPIO3 pin is configured as an input pin.
GPIO2 Pin IO Configuration
When this bit = 1, the GPIO2 pin is configured as an output pin.
When this bit = 0 (default), the GPIO2 pin is configured as an input pin.
GPIO1 Pin IO Configuration
When this bit = 1, the GPIO1 pin is configured as an output pin.
When this bit = 0 (default), the GPIO1 pin is configured as an input pin.
MD[3] Status MD[2] Status
MD[11] MD[10]
Status Status
GPIO3 Pin GPIO2 Pin
IO Config. IO Config.
Pin Function
MA10
GPIO1 GPIO2
GPIO1 GPIO2
GPIO1 GPIO2
MA10
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MD[1] Status MD[0] Status
MD[9] MD[8]
Status Status
GPIO1 Pin
n/a
IO Config.
MA11
MA11
Hardware Functional Specification
Issue Date: 01/02/02
RO
RO
RW